tangxifan
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7cfc50aa8f
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[vtr] update engin
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2022-09-18 21:46:06 -07:00 |
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tangxifan
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d1334ef8c9
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[engine] update vtr
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2022-09-18 10:58:37 -07:00 |
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tangxifan
|
76720dfe16
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[engine] update vtr
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2022-09-18 10:05:30 -07:00 |
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tangxifan
|
370ddcc1ed
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[engine] update vtr
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2022-09-17 22:24:07 -07:00 |
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tangxifan
|
fa2cc87d0a
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[engine] update vtr
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2022-09-17 10:25:33 -07:00 |
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tangxifan
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4dd90f4466
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[engine] update vtr
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2022-09-17 10:22:41 -07:00 |
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tangxifan
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29fff9e139
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[engine] update vtr
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2022-09-17 09:57:25 -07:00 |
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tangxifan
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fcf4525870
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[engine] update vtr
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2022-09-17 09:52:33 -07:00 |
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tangxifan
|
9e8c6be408
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[engine] update vtr
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2022-09-16 21:42:48 -07:00 |
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tangxifan
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373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
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e98d022d3a
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[engine] update vtr
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2022-09-16 16:23:14 -07:00 |
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tangxifan
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30988d7072
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Merge pull request #794 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-16 13:59:48 -07:00 |
github-actions[bot]
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d3019c1642
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Updated Patch Count
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2022-09-16 20:28:38 +00:00 |
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tangxifan
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b7b82804ff
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Merge pull request #792 from lnis-uofu/io_indexing
Now I/O indexing follows a natural way (clockwise) throughout the fabric.
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2022-09-16 12:01:25 -07:00 |
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tangxifan
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a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
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f0fe781dbc
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[engine] fixed a bug
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2022-09-16 10:45:27 -07:00 |
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tangxifan
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a2e22787c2
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[test] deploy the new test cases to the basic regression tests
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2022-09-16 10:31:15 -07:00 |
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tangxifan
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10e86d334a
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[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
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f2e13e5ea9
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[arch] add more flexible layout to test I/O center features
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2022-09-16 10:00:08 -07:00 |
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tangxifan
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bba5b7b070
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[engine] syntax
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2022-09-15 23:04:37 -07:00 |
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tangxifan
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cbc71c75c4
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[engine] now io indexing follows a natural way
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2022-09-15 23:01:35 -07:00 |
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tangxifan
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b0b3d52e66
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Merge pull request #787 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-14 19:42:01 -07:00 |
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github-actions[bot]
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7903bb40f0
|
Updated Patch Count
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2022-09-15 02:39:51 +00:00 |
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tangxifan
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7016c9e4c8
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Merge pull request #785 from lnis-uofu/io_center
Support I/Os in the center of the FPGA fabric
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2022-09-14 18:34:28 -07:00 |
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tangxifan
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7424b59de1
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Merge pull request #786 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-14 17:32:22 -07:00 |
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tangxifan
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8378ad4bf3
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[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
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2022-09-14 17:13:23 -07:00 |
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github-actions[bot]
|
2b2fc6020d
|
Updated Patch Count
|
2022-09-15 00:02:45 +00:00 |
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tangxifan
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036933dc14
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[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
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2022-09-14 16:46:10 -07:00 |
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tangxifan
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0425b00af5
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[engine] fixed a bug for frame-based protocols
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2022-09-14 16:41:30 -07:00 |
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tangxifan
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cb89488f76
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[engine] now support a custom list for indexing I/O children in each module
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2022-09-14 15:54:55 -07:00 |
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tangxifan
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ec38b3990f
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[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
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0781f1ca3b
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Merge branch 'io_center' of github.com:lnis-uofu/OpenFPGA into io_center
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2022-09-14 11:31:03 -07:00 |
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tangxifan
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eb8b7e6901
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[engine] fixed a bug in i/o indexing
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2022-09-14 11:30:34 -07:00 |
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tangxifan
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83c89ae1bf
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[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
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330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
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a37e270f25
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[arch] now custom I/O loc test case cover I/Os in the center of the fabric
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2022-09-13 16:57:18 -07:00 |
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tangxifan
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18cf3615ea
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Merge pull request #780 from lnis-uofu/rst_lut_in
Test reset signal from a global network to drive an LUT input
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2022-09-12 18:22:03 -07:00 |
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tangxifan
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48f776d49b
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[doc] update documentation about the new option
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2022-09-12 16:58:32 -07:00 |
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tangxifan
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1c2192a87d
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[engine] fixed a few bugs
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2022-09-12 16:50:32 -07:00 |
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tangxifan
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0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
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2fc124e109
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[engine] now repack has a new option "--ignore_global_nets_on_pins"
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2022-09-12 16:18:26 -07:00 |
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tangxifan
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a3d070ac6f
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
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tangxifan
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314f5395b4
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[benchmark] fixed a bug which causes yosys failed
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2022-09-09 17:04:59 -07:00 |
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tangxifan
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91fe27ff66
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[test] deploy new test to ci
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2022-09-09 17:00:28 -07:00 |
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tangxifan
|
1ab7590603
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[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
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tangxifan
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cc974a80f7
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[arch] added a new architecture to test the local routing architecture where reset is on LUT
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2022-09-09 16:48:10 -07:00 |
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tangxifan
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7a38c7dd18
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[benchmark] add a new benchmark to test reset signal to drive both lut and ff
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2022-09-09 16:42:55 -07:00 |
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tangxifan
|
266da6dd4c
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[engine] update vtr
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2022-09-09 15:02:46 -07:00 |
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tangxifan
|
8bd55babb0
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[engine] update vtr
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2022-09-09 15:00:22 -07:00 |
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tangxifan
|
95d7a17b3c
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Merge branch 'master' into vtr_upgrade
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2022-09-09 14:32:42 -07:00 |