4 Commits

Author	SHA1	Message	Date
tangxifan	663b1b7665	refactorint net addition for configuration signals in module graph	2019-10-11 13:07:14 -06:00
tangxifan	6bed89c237	refactored counting config bits for circuit model and update Verilog generation for primitive pb_types	2019-10-08 18:00:04 -06:00
tangxifan	433fc73460	refactored local encoder support for Verilog MUX generation	2019-09-27 23:10:43 -06:00
tangxifan	dbe1625267	Refactored Verilog wiring for formal verification ports in Switch Blocks	2019-09-27 13:51:22 -06:00