tangxifan
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42f85004b6
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
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3c0ef2067d
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fixed critical bugs in pass_tracks identification and update regression test for tileable arch
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2019-06-25 21:59:38 -06:00 |
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tangxifan
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4d3b5f12b4
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fixed bugs for UNIVERSAL and WILTON switch blocks
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2019-06-25 14:15:29 -06:00 |
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tangxifan
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785b560bd5
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sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
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2019-06-24 22:46:56 -06:00 |
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tangxifan
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fd301eeb66
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many bug fixing and now start improving the routability of tileable rr_graph
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2019-06-24 17:33:29 -06:00 |
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tangxifan
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0d62661c71
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bug fixing and spot critical bugs in directlist parser
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2019-06-23 20:52:38 -06:00 |
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tangxifan
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cdd4af9c58
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vpr likes the tileable rr_graph while fpga_x2p does not
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2019-06-23 18:11:13 -06:00 |
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tangxifan
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59df305668
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bug fixing and reorganize rr_graph builder source files
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2019-06-23 16:40:13 -06:00 |
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tangxifan
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2837f44df2
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bug fixing for tileable rr_graph generator.
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2019-06-22 20:41:06 -06:00 |
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tangxifan
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7c38b32eb1
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keep bug fixing for tileable rr_graph generator
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2019-06-21 22:51:11 -06:00 |
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tangxifan
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41954056ce
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many bug fixing for tileable rr_graph generator. Still debugging
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2019-06-21 17:58:46 -06:00 |
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tangxifan
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d48fd959a9
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keep bug fixing for tileable rr_graph generator
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2019-06-20 22:30:26 -06:00 |
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tangxifan
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548242b368
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plug-in tileable rr generator which can be enable by a XML property
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2019-06-20 21:06:26 -06:00 |
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tangxifan
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baab9c4a21
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basically finished the coding of tileable rr_graph generator. testing to go
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2019-06-20 18:17:07 -06:00 |
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tangxifan
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2f15d2d13c
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keep developing tileable rr_graph, track2ipin and opin2track to go
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2019-06-19 21:30:16 -06:00 |
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tangxifan
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ba15358564
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developing ipin2track mapping for tiles
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2019-06-18 18:06:21 -06:00 |
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tangxifan
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9ca1b42f4c
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developing switch block pattern for tileable routing architecture
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2019-06-18 16:52:42 -06:00 |
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tangxifan
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352c97302b
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start building object GSB graph
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2019-06-17 22:10:30 -06:00 |
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tangxifan
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f4191315da
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use rr_gsb to build edges of rr_graph
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2019-06-17 18:01:45 -06:00 |
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tangxifan
|
51ff150a77
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bug fixing in tileable rr_graph generator
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2019-06-17 10:16:08 -06:00 |
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tangxifan
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0d14fef53e
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bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
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2019-06-16 23:02:18 -06:00 |
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tangxifan
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1af3b5ef55
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set chan_rr_nodes in tileable rr_graph builder
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2019-06-16 14:23:19 -06:00 |
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tangxifan
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8c9cc003ea
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developing routing track rr_node set up in tileable routing architecture
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2019-06-15 18:11:08 -06:00 |
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tangxifan
|
d3296d0975
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developing tileable rr_graph builder
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2019-06-14 22:35:42 -06:00 |
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tangxifan
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a33627606e
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developing tileable routing track arrangement
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2019-06-14 17:35:40 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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tangxifan
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5ae4dec0af
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fix bugs in CMakeList on enable/disable VPR Graphics
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2019-06-12 22:48:00 -06:00 |
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tangxifan
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1d00e3665b
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start developing tileable_rr_graph_builder
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2019-06-11 16:50:40 -06:00 |