Commit Graph

1188 Commits

Author SHA1 Message Date
Ganesh Gore 632c9d6976 Added python execution path in config file 2019-08-25 00:42:48 -06:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
tangxifan 3fb3082447 add more tests 2019-08-23 14:10:01 -06:00
Ganesh Gore 52d6a9e979 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-23 13:41:29 -06:00
Ganesh Gore 28dde899db Updated Architecture Template 2019-08-23 12:44:45 -06:00
tangxifan 520630c5e2 add more testing tasks 2019-08-23 10:16:52 -06:00
Ganesh Gore 6e7de16ad4 Solved bug in commnad rearrangement 2019-08-22 23:41:25 -06:00
Ganesh Gore 89589ddc1c Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-22 18:46:51 -06:00
Ganesh Gore 77e2a7bca3 Added execution time logs in flow script 2019-08-22 17:01:38 -06:00
Ganesh Gore 30cbe38d3d Added Test Modes - Added blif VPR Option 2019-08-22 17:00:59 -06:00
Ganesh Gore d5ce1b557e Made thread logs prettier 2019-08-22 16:56:58 -06:00
Ganesh Gore 764d7039b5 Import utils bug fixing for travis test 2019-08-21 12:42:58 -06:00
Ganesh Gore 2f0acfad23 Updated travis to run regression task 2019-08-21 11:09:53 -06:00
Ganesh Gore e51ff44710 Added execution time information in logs 2019-08-21 11:08:47 -06:00
Ganesh Gore a335a57c6c Added debug option to commnad line arguments 2019-08-21 11:08:13 -06:00
tangxifan 59f1ac7310 add missing files and try to refactor submodule essential 2019-08-20 20:49:26 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 60e8d2b29f add missing files and try to refactor submodule essential 2019-08-20 16:13:08 -06:00
Ganesh Gore b7484ef178 Removed traces of old template file 2019-08-20 15:58:19 -06:00
Ganesh Gore afee2229af Removed unused templates and file from openfpga_flow directory 2019-08-19 21:32:52 -06:00
Ganesh Gore 08b0ef3550 Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
Ganesh Gore 53941eaf5c Changed yosys output file name 2019-08-19 19:06:46 -06:00
Ganesh Gore 8d0153d34e Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
Ganesh Gore 616d7706c9 Added list of intermidiate files filename 2019-08-19 19:05:08 -06:00
Ganesh Gore 8f8707ff98 Added option to filter results after parsing 2019-08-19 19:04:14 -06:00
Ganesh Gore 5116aa2ae1 Added architecture and replaced variables 2019-08-19 19:02:50 -06:00
Ganesh Gore cb5b16c949 Moved required files to openfpga folder 2019-08-19 18:57:42 -06:00
Ganesh Gore 6dc05b769b Added Power Model Files 2019-08-19 18:55:23 -06:00
Ganesh Gore 7f6c1b3e00 Code re-arrangement
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
Ganesh Gore 12c998c12a Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
Ganesh Gore 66bb8a5e4b Updated RRAM architecture file 2019-08-17 02:20:04 -06:00
Ganesh Gore 7bfc48b8e4 Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
Ganesh Gore c43c3cdf25 Added VPR output parse option 2019-08-16 13:36:39 -06:00
Ganesh Gore effbd332aa Added task report generation 2019-08-16 10:59:44 -06:00
Ganesh Gore 901932a4fc First draft: Working openfpga task flow 2019-08-16 09:44:50 -06:00
Ganesh Gore 5d3708651e Added fpga_flow and fpga_task script
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
Ganesh Gore 9ab57d1b2e Added fpga_flow script - Working Yosys 2019-08-09 16:49:05 -06:00
Ganesh Gore b82369dd96 Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00