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1188 Commits

Author SHA1 Message Date
tangxifan 978c60e75b [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 13:29:38 -07:00
tangxifan 18bab18032 [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release 2021-10-30 13:20:58 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 94328351be [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts 2021-10-30 12:00:06 -07:00
tangxifan 0a449cc24c [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected 2021-10-30 11:45:01 -07:00
tangxifan 9c06041ce4 [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` 2021-10-30 11:27:40 -07:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan b8d5920529 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-28 15:45:58 -07:00
Aram Kostanyan 2eef21a1af Fixed port names for mult_36x36 2021-10-26 19:14:43 +05:00
nadeemyaseen-rs 274252438a Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-20 20:13:46 +05:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
nadeemyaseen-rs e0cfd46ec7 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-14 19:25:31 +05:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan 2bf203cd00 [Test] Deploy the new test to basic regression test 2021-10-11 09:54:39 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan cdcb07256b [Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization 2021-10-11 09:49:22 -07:00
tangxifan 982a324e0d [Test] Temporarily disable some tests; Will go back later 2021-10-10 23:30:50 -07:00
tangxifan 40fd89fdb4 [arch] Update fabric key for multi-region 2021-10-10 22:03:49 -07:00
tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test 2021-10-09 20:45:23 -07:00
tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank 2021-10-09 20:44:28 -07:00
tangxifan 82e77b42c5 [Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA 2021-10-09 20:43:55 -07:00
tangxifan 8aa2647878 [Script] Bug fix in slow clock frequency in shift register chain contraints 2021-10-06 16:49:01 -07:00
tangxifan dc5aedc393 [Script] Correct naming for clocks in shifter register chain defined in simulation setting files 2021-10-06 13:36:35 -07:00
tangxifan a1eaacf5a8 [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency 2021-10-06 12:12:15 -07:00
tangxifan 554018449e [Test] Update regression test script 2021-10-06 12:10:37 -07:00
tangxifan b98a8ec718 [Test] Added the dedicated test case for fixed shift register clock frequency 2021-10-06 12:09:26 -07:00
tangxifan 169bb5fa45 [Script] Add an example simulation setting file with a fixed clock frequency for shift registers 2021-10-06 11:58:50 -07:00
tangxifan 189ade6c1e [Test] Bug fix 2021-10-05 19:17:34 -07:00
tangxifan f74ea5d39a [Test] Use the new openfpga shell script in don't care bit tests 2021-10-05 19:14:44 -07:00
tangxifan 4add9781d5 [Script] Add a new openfpga shell script for don't care bits outputting 2021-10-05 19:13:50 -07:00
tangxifan 50604e4589 [Test] move test cases 2021-10-05 19:02:43 -07:00
tangxifan 064ac478f3 [Test] Deploy news test to fpga-bitstream regression tests 2021-10-05 19:01:03 -07:00
tangxifan fed6c133b1 [Test] Add new tests to validate the correctness of bitstream files with don't care bits 2021-10-05 18:59:33 -07:00
tangxifan 80fd1efd61 [Test] Add an example test key for multi-region QuickLogic memory bank using shift registers 2021-10-05 11:46:58 -07:00
tangxifan b21f212031 [Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key 2021-10-05 11:39:53 -07:00
tangxifan 492db50efe [Test] Deploy the new test to basic regression tests 2021-10-05 10:59:26 -07:00
tangxifan 52569f808e [Test] Added a test case for QuickLogic memory bank using shift registers in multiple region 2021-10-05 10:57:33 -07:00
tangxifan d2859ca1c8 [Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers 2021-10-05 10:56:20 -07:00
tangxifan fbef22b494 [Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers 2021-10-04 16:39:53 -07:00
tangxifan 13c31cb89c [Test] Deploy the qlbanksr_wlr to basic regression tests 2021-10-04 16:37:49 -07:00
tangxifan fa1908511d [Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control 2021-10-04 16:36:20 -07:00
tangxifan 7f75c2b619 [Test] Deploy shift register -based QL memory bank test case to basic regression test 2021-10-03 16:06:44 -07:00
tangxifan 86e7c963f8 [Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files 2021-10-02 22:19:20 -07:00
tangxifan 0b06820177 [HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals 2021-10-01 17:06:35 -07:00
tangxifan 7ba5d27ea7 [Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model 2021-10-01 17:02:35 -07:00
tangxifan ff6f7e80f6 [Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers 2021-10-01 16:52:06 -07:00
tangxifan dda147e234 [Flow] Add an example simulation setting file for defining programming shift register clocks 2021-10-01 11:04:23 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan fa57117f50 [Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers 2021-10-01 10:19:51 -07:00
tangxifan 41cc375746 [Arch] define default CCFF model in ql bank example architecture that uses shift registers 2021-09-29 16:34:40 -07:00
tangxifan 89a97d83bd [Test] Added a new test case for the shift register banks in QuickLogic memory banks 2021-09-29 16:28:06 -07:00
tangxifan 4968f0d11f Merge branch 'master' into qlbank_sr 2021-09-28 14:20:30 -07:00
tangxifan 80232fc459 [Arch] Add a new example architecture for QL memory bank using WLR in shift registers 2021-09-28 12:36:36 -07:00
tangxifan 4c04c0fbd7 [Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models 2021-09-28 12:35:42 -07:00
tangxifan 2ce2fb269a [HDL] Added a different FF model which is designed to drive WLW only 2021-09-28 12:35:13 -07:00
tangxifan 6469ee3048 [HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs 2021-09-28 12:21:54 -07:00
tangxifan 4400dae108 [Test] Bug fix in the wrong arch name 2021-09-28 11:40:25 -07:00
tangxifan 4aed045cdd [Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs 2021-09-28 11:34:20 -07:00
tangxifan 811c898173 [Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests 2021-09-28 11:29:45 -07:00
tangxifan dae3554fd4 [Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals 2021-09-28 11:27:49 -07:00
tangxifan 1ca1b0f3e9 [Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests 2021-09-22 15:58:05 -07:00
tangxifan 655b195d8b [Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level 2021-09-22 15:56:44 -07:00
tangxifan a98df811ed [Arch] Bug fix: wrong circuit model name was used for CCFF 2021-09-22 15:50:47 -07:00
tangxifan 53da5d49fe [Arch] Correct XML syntax errors 2021-09-22 15:48:14 -07:00
tangxifan 3cfd5c3531 [Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks 2021-09-22 15:04:59 -07:00
tangxifan 212c5bd642 [Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization 2021-09-22 15:04:19 -07:00
tangxifan b0aaab9c03 [Test] Bug fix due to mismatches in device layout between fabric key and VPR settings 2021-09-22 11:32:13 -07:00
tangxifan efed268585 [Test] Deploy new test (for multi-region QL memory bank) to basic regression tests 2021-09-22 11:30:08 -07:00
tangxifan abfa380333 [Test] Added a test case to validate the fabric key of 2-region QL memory bank 2021-09-22 11:27:09 -07:00
tangxifan 337ed33b68 [Test] Added a sample fabric key for 2-region QL memory bank 2021-09-22 11:25:16 -07:00
tangxifan 7db7e2d8f6 [Test] Deploy the new test case for multi region QL memory bank to basic regression tests 2021-09-22 10:05:27 -07:00
tangxifan d0fe12fadd [Arch] Add an example OpenFPGA architecture for 2-region QL memory bank 2021-09-22 10:03:39 -07:00
tangxifan 51fc222d61 [Test] Added a new test case for multi-region QL memory bank 2021-09-22 10:01:33 -07:00
tangxifan ab42239b94 [Test] Bug fix in the fabric key 2021-09-21 16:44:58 -07:00
tangxifan f57aceff87 [Test] Deploy the load external key test case for ql memory bank to basic regression tests 2021-09-21 16:25:14 -07:00
tangxifan aad47ffbc6 [Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric 2021-09-21 16:22:50 -07:00
tangxifan 1412121541 [Test] Added a new test to validate the fabric key parser for QL memory bank 2021-09-21 16:20:24 -07:00
tangxifan cd0d8b86fa [Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank 2021-09-21 15:55:34 -07:00
tangxifan 7327850cf3 [Test] Deploy the fabric key test case for ql memory bank to basic regression tests 2021-09-21 15:43:54 -07:00
tangxifan dc2d1d1c3c [Test] Add a new test case to validate the correctness of fabric key file for ql memory bank 2021-09-21 15:42:20 -07:00
tangxifan d36d1ebee2 [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan 3f6ac41868 [Test] Deploy the WLR test to the basic regression tests 2021-09-20 11:21:58 -07:00
tangxifan 60fc3ab36c [Test] Added a new test case for the WLR memory bank 2021-09-20 11:20:36 -07:00
tangxifan 5c1c428ea5 [HDL] Updated cell library with the SRAM cell with Read Enable signal 2021-09-20 11:13:36 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
slt b867db815f
Update fpgaflow_default_tool_path.conf 
Update regex for VPR
 2021-09-17 14:02:26 +08:00
tangxifan 81a2ad58df [Test] Deploy the ql memory bank test case to basic regression tests (run on CI) 2021-09-09 13:48:30 -07:00
tangxifan b82cfdf555 [Test] Add the QL memory bank test to regression test cases 2021-09-09 09:29:21 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan 6adf439081 Merge remote-tracking branch 'upstream/master' 2021-09-01 14:19:00 -07:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00