Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
tangxifan
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5a6874e9f1
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[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
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2021-07-02 17:28:17 -06:00 |
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tangxifan
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0b6a9b06f5
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[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
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2021-07-02 10:39:07 -06:00 |
ANDREW HARRIS POND
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1d281765ea
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fixed tab spacing
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2021-07-01 16:42:04 -06:00 |
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ANDREW HARRIS POND
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808821bb8c
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fixed errors
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2021-07-01 16:40:03 -06:00 |
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ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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tangxifan
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a898537474
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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
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2021-06-30 15:29:13 -06:00 |
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tangxifan
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4d4577bb83
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[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
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2021-06-30 15:13:47 -06:00 |
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tangxifan
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477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
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0a0d10b36d
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[HDL] Bug fix in Verilog syntax
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2021-06-22 16:18:46 -06:00 |
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tangxifan
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07dcf3ad27
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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Andrew Pond
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3cfc42cdf9
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added testbench CI
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2021-06-15 14:16:31 -06:00 |
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Andrew Pond
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12b44e0eca
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added configuration benchmark files
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2021-05-13 10:04:23 -06:00 |
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tangxifan
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16fff90607
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[Benchmark] Add microbenchmark 1-bit blinking
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2021-05-06 15:17:27 -06:00 |
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tangxifan
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a571b063b6
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[Benchmark] Add 1k DPRAM benchmark which can fit new arch
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2021-04-28 11:26:31 -06:00 |
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tangxifan
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7d059f7407
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[Benchmark] Bug fix in dual port ram 16k benchmark
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2021-04-27 23:33:20 -06:00 |
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tangxifan
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3c1c33bf1e
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[Benchmark] Add a microbenchmark just fit 16k dual port ram
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2021-04-27 22:51:43 -06:00 |
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tangxifan
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7e2368158e
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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tangxifan
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5a85ec9fa0
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[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
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2021-04-27 22:09:10 -06:00 |
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tangxifan
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1d498bb296
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[Benchmark] Add a scalable micro benchmark fifo
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2021-04-27 15:26:52 -06:00 |
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tangxifan
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200b6d39a6
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[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
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2021-04-23 20:36:28 -06:00 |
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tangxifan
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671394ec2c
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[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
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2021-04-23 20:33:43 -06:00 |
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tangxifan
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b203ef7bc2
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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tangxifan
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c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
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bbdc0e53af
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[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
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2021-04-16 20:14:48 -06:00 |
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tangxifan
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e46c6e75a3
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[Benchmark] Add missing RTL for IWLS2005 benchmarks
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2021-04-16 16:50:41 -06:00 |
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tangxifan
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26d3b5a954
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[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
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2021-04-16 16:08:58 -06:00 |
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tangxifan
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86ad572530
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[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 14:27:54 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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be03eafd66
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[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
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2021-03-23 15:33:37 -06:00 |
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tangxifan
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55d1004cf2
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[Benchmark] Add missing DPRAM module to LU32PEEng
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2021-03-22 14:41:38 -06:00 |
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tangxifan
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5fc83ebea3
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[Benchmark] Add missing DPRAM modules to LU8PEEng
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2021-03-22 14:38:00 -06:00 |
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tangxifan
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b828f91a78
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[Benchmark] Add missing DPRAM and SPRAM modules to mcml
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2021-03-22 14:13:05 -06:00 |
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tangxifan
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b906ab814e
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[Benchmark] Add missing DPRAM module to mkPktMerge
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2021-03-22 12:51:23 -06:00 |
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tangxifan
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310c2a9495
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[Benchmark] Add missing DPRAM module to mkDelayWorker32B
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2021-03-22 12:51:02 -06:00 |
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tangxifan
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707247283c
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[Benchmark] Add missing DPRAM module to mkSMAdapter4B
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2021-03-22 12:50:39 -06:00 |
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tangxifan
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eb056e2afd
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[Benchmark] Add missing DPRAM module to or1200
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2021-03-22 12:50:17 -06:00 |
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tangxifan
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169ee53b79
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[Benchmark] Add missing modules to VTR benchmarks
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2021-03-20 22:53:17 -06:00 |
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tangxifan
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2bd8ef2af9
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[Benchmark] Patch boundtop.v with missing SPRAM module
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2021-03-20 21:00:53 -06:00 |
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tangxifan
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6bf4880c50
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[benchmark] Add vtr benchmark
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2021-03-17 15:24:26 -06:00 |
Tarachand Pagarani
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ce76c58422
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add shift register test case
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2021-03-05 09:06:05 -08:00 |
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tangxifan
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2dbdc2644f
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[Benchmark] Remove replicate micro benchmarks
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2021-02-22 10:22:19 -07:00 |
Lalit Narain Sharma
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be5e0cdea9
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Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
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2021-02-22 09:50:26 +05:30 |
Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
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Lalit Sharma
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d4c5a5655a
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Removing blif file as well as and2 testcase
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2021-02-19 08:55:17 -08:00 |
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tangxifan
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1f097abe99
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |