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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 73386dd1a9 refactored the Verilog header generation 2019-12-04 17:55:05 -07:00
tangxifan 9cf8683acd add module generation for memories 2019-10-22 15:31:08 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00