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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 8ec8ac4118 bug fixed in flatten memory organization. Passed verification 2020-06-11 19:31:12 -06:00
tangxifan 25e0583636 add io location map data structure and start porting verilog testbench generator 2020-02-26 17:10:57 -07:00
tangxifan 0d5292ad0d adapt verilog writer utils 2020-02-15 23:26:59 -07:00