tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
|
tangxifan
|
e456b6f905
|
replace spice_models with circuit model in bitstream generator
|
2019-08-16 16:36:49 -06:00 |
|
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
|
tangxifan
|
b66e120366
|
patch on local encoders for unused configuration, avoid chip-burn issues
|
2019-08-16 15:32:23 -06:00 |
|
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
AurelienUoU
|
8e38aa6019
|
Merge with heterogeneous for unfracturable LUT bug fix
|
2019-08-14 10:10:27 -06:00 |
|
AurelienUoU
|
df873903f8
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
|
AurelienUoU
|
30c0f2b6b7
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-14 09:11:54 -06:00 |
|
AurelienUoU
|
90aaed6e1f
|
Fix regression test
|
2019-08-14 09:10:13 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
|
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
|
2019-08-13 15:37:42 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
AurelienUoU
|
8dab4dec90
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-13 11:09:29 -06:00 |
|
AurelienUoU
|
7851246424
|
Resolve merge issue
|
2019-08-13 11:08:30 -06:00 |
|
tangxifan
|
c56f289d3e
|
add checkers for circuit library
|
2019-08-12 16:45:33 -06:00 |
|
tangxifan
|
d4ae160d3a
|
start adding circuit library checkers
|
2019-08-12 14:20:11 -06:00 |
|
AurelienUoU
|
2da4d3f33c
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-12 09:57:02 -06:00 |
|
tangxifan
|
fbdab32a2d
|
timing graph for circuit models are working
|
2019-08-10 13:03:24 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
2c7d6e3de4
|
adding port parsers
|
2019-08-09 17:48:55 -06:00 |
|
tangxifan
|
f80e58c753
|
developing a in-house tokenizer
|
2019-08-09 16:36:22 -06:00 |
|
tangxifan
|
3d7adb3dd9
|
start developing parsers for delay values
|
2019-08-09 15:52:28 -06:00 |
|
tangxifan
|
6b5ac2e1ef
|
add timing graph builder for circuit models
|
2019-08-09 12:45:03 -06:00 |
|
tangxifan
|
c8d04c4f00
|
plug in fast look-up builder
|
2019-08-08 21:20:28 -06:00 |
|
tangxifan
|
158c67075e
|
built a conversion from spice_models to circuit_library and plug in
|
2019-08-08 17:25:27 -06:00 |
|
tangxifan
|
e19485bbb7
|
add more accessors and more to be added when plug into framework
|
2019-08-08 14:16:29 -06:00 |
|
tangxifan
|
ad8c33e1ba
|
complete the mutators
|
2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
5b0c9572c3
|
add mutators for delay_info
|
2019-08-07 21:19:16 -06:00 |
|
tangxifan
|
03a64e2ad8
|
complete the mutators for ports
|
2019-08-07 20:54:27 -06:00 |
|
tangxifan
|
9f8c7a3fc7
|
adding port mutators
|
2019-08-07 17:47:39 -06:00 |
|
tangxifan
|
ed4642a23f
|
adding basic mutators
|
2019-08-07 17:12:05 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
|
2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
|
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
33f3a991b5
|
init effort to start developing mux local encoders
|
2019-08-06 14:17:55 -06:00 |
|
AurelienUoU
|
40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-29 11:45:23 -06:00 |
|
tangxifan
|
32e3a556b9
|
bug fixing herited from explicit mapping
|
2019-07-17 09:26:05 -06:00 |
|
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
|
2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
|
2019-07-17 08:36:09 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
|
2019-07-17 07:54:23 -06:00 |
|
tangxifan
|
e9154b1f74
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 14:42:45 -06:00 |
|
tangxifan
|
115411941b
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 13:15:45 -06:00 |
Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
Baudouin Chauviere
|
e602006a07
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-16 12:45:13 -06:00 |
|
AurelienUoU
|
b810b5cab9
|
fpga_flow bug fix + upload k8 architecture
|
2019-07-16 07:04:45 -06:00 |
|
AurelienUoU
|
35e1962732
|
Merge branch 'dev' into documentation
|
2019-07-15 21:19:26 -06:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |
|
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |
|
tangxifan
|
b690e702f6
|
adding more info to show the progress bar in backannotating GSBs
|
2019-07-13 19:53:44 -06:00 |
|
tangxifan
|
aa4cd850ae
|
try to optimize the runtime of routing uniqueness detection
|
2019-07-13 18:10:34 -06:00 |
|
tangxifan
|
78578f66c5
|
bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
|
2019-07-13 14:48:32 -06:00 |
|
AurelienUoU
|
19ccbce9d0
|
Rename option to use circuit_model rather than spice_model
|
2019-07-12 16:18:28 -06:00 |
|
AurelienUoU
|
ef600bc63f
|
Save workspace
|
2019-07-12 15:57:41 -06:00 |
|
Baudouin Chauviere
|
f140e08093
|
Pre-Merge modifications
|
2019-07-12 10:48:43 -06:00 |
|
Baudouin Chauviere
|
a0f1f8d163
|
Fix when explicit verilog is NOT used
|
2019-07-12 10:39:31 -06:00 |
|
tangxifan
|
f0ecc51b51
|
bug fixing to resolve the conflicts between explicit port map and standard cell map
|
2019-07-12 10:38:20 -06:00 |
|
AurelienUoU
|
e65cf9f5fd
|
Update ERI-demo
|
2019-07-12 08:55:19 -06:00 |
|
Baudouin Chauviere
|
40d3460bac
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-11 22:13:30 -06:00 |
|
Baudouin Chauviere
|
e461cd0b99
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-11 22:09:49 -06:00 |
|
Baudouin Chauviere
|
1431ee2f82
|
Fix Explicit verilog
|
2019-07-11 22:09:34 -06:00 |
|
tangxifan
|
cffdebd912
|
bug fixed for the tileable RR graph generator for heterogeneous blocks
|
2019-07-11 21:02:09 -06:00 |
|
Baudouin Chauviere
|
c9b84f61c9
|
Hot fix
|
2019-07-11 17:39:02 -06:00 |
|
Baudouin Chauviere
|
d0cd5a2bc1
|
Hot fix
|
2019-07-11 17:27:31 -06:00 |
|
tangxifan
|
9c203ca4d2
|
bug fixing in SDC generator
|
2019-07-11 17:10:08 -06:00 |
|
Baudouin Chauviere
|
f4be375637
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
tangxifan
|
31749fe62b
|
fix bugs in fpga_flow.pl
|
2019-07-10 21:12:00 -06:00 |
|
tangxifan
|
a90316e9f4
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 15:13:46 -06:00 |
|
tangxifan
|
acee0161c7
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 15:13:24 -06:00 |
|
Baudouin Chauviere
|
6441f2ebe7
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 14:16:55 -06:00 |
|
Baudouin Chauviere
|
0a978db866
|
Fix regression test
|
2019-07-10 14:16:34 -06:00 |
|
tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
|
tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
|
tangxifan
|
57ae5dbbec
|
bug fixing for rectangle FPGA sizes
|
2019-07-09 20:47:52 -06:00 |
|
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |
|
tangxifan
|
737cc2874f
|
Merge branch 'tileable_routing' into dev
|
2019-07-09 17:42:44 -06:00 |
|
tangxifan
|
65f696c1d7
|
fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
|
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
|
Baudouin Chauviere
|
792ba23f4f
|
Correction pre-merge
|
2019-07-09 14:34:34 -06:00 |
|
Baudouin Chauviere
|
589f58b55e
|
Regression test succeeded
|
2019-07-09 09:18:06 -06:00 |
|
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
tangxifan
|
5d5e09fcdb
|
minor fix in trying to accelerate the unique routing functions
|
2019-07-08 17:12:36 -06:00 |
|
Baudouin Chauviere
|
df0a3d23a3
|
Correction top module
|
2019-07-08 10:23:14 -06:00 |
|
Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
|
tangxifan
|
76fefdb876
|
bug fixing in Fc_in and be serious in the performance of rr_graph
|
2019-07-05 16:23:15 -06:00 |
|
tangxifan
|
c62762ce59
|
bug fixing in assign ipins to tracks using Fc_in
|
2019-07-05 13:42:22 -06:00 |
|
tangxifan
|
64d8e9663a
|
minor fix to satisfy Fc_in and Fc_out
|
2019-07-05 13:13:35 -06:00 |
|
tangxifan
|
3077efa74f
|
add option to compact tileable routing arch
|
2019-07-04 17:13:34 -06:00 |
|
tangxifan
|
d64aeef5c4
|
add profiling to routing compact process
|
2019-07-03 16:57:34 -06:00 |
|
tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
|
2019-07-03 16:46:43 -06:00 |
|
tangxifan
|
b79d276ea9
|
add profiling to fpga_x2p_setup
|
2019-07-03 14:44:54 -06:00 |
|
tangxifan
|
d5137eb424
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-03 14:31:18 -06:00 |
|
tangxifan
|
5195faab8b
|
Merge branch 'dev' into tileable_routing
|
2019-07-03 14:30:39 -06:00 |
|
tangxifan
|
4f3cb0bdf3
|
added tileable routing chanW adaption to fixed W router
|
2019-07-03 14:29:50 -06:00 |
Ganesh Gore
|
443a73954f
|
Removed all local files
+ Removed local configurations and scripts from previous commit
|
2019-07-03 14:26:06 -06:00 |
|
Ganesh Gore
|
57ad71438b
|
Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
|
2019-07-03 13:39:52 -06:00 |
|
tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
|
2019-07-03 12:11:48 -06:00 |
|
tangxifan
|
02398818a9
|
update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
|
2019-07-03 10:33:02 -06:00 |
|
tangxifan
|
4392c6bc3a
|
bug fixing in fpga_flow scripts and add more print-out message for VPR
|
2019-07-02 15:34:59 -06:00 |
|
Baudouin Chauviere
|
b08513d902
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
|
2019-07-02 10:00:02 -06:00 |
|
tangxifan
|
44301bfd77
|
updated SPICE generator to avoid issues on clb2clb_direct
|
2019-07-02 09:01:52 -06:00 |
|
tangxifan
|
5b25bbb120
|
bug fixed for direct connection in CBs and direct connection in top netlist
|
2019-07-01 17:25:00 -06:00 |
|
Baudouin Chauviere
|
f189ef1d8f
|
Done with the submodules
|
2019-07-01 14:24:09 -06:00 |
|
Baudouin Chauviere
|
370ce23646
|
Mux explicit verilog done
|
2019-07-01 13:58:24 -06:00 |
|
Baudouin Chauviere
|
863e8677c0
|
Further add new functions to tree
|
2019-07-01 12:12:36 -06:00 |
|
Baudouin Chauviere
|
0e04b88c8f
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
|
tangxifan
|
1332ba62e8
|
update tileable rr_graph generator to improve routability and also enable assoicated testing
|
2019-06-27 17:52:25 -06:00 |
|
tangxifan
|
15c536e9b4
|
minor fixing in printing the rr_node stats
|
2019-06-27 16:34:21 -06:00 |
|
Baudouin Chauviere
|
04eb6d3488
|
Correction pre-merge
|
2019-06-27 14:33:06 -06:00 |
|
Ganesh Gore
|
11e6350214
|
Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev
|
2019-06-27 14:22:40 -06:00 |
|
Baudouin Chauviere
|
7c742f1cbb
|
Stable, is_explicit propagated through the code. Not implemented though except for muxes
|
2019-06-27 10:29:57 -06:00 |
|
tangxifan
|
8edd85c9fc
|
keep fixing bugs in verilog SDC generator for tileable CBs
|
2019-06-26 22:58:52 -06:00 |
|
tangxifan
|
711e369fe7
|
fixing bugs in the SDC generator and report_timing
|
2019-06-26 18:09:09 -06:00 |
|
tangxifan
|
0fe54d87d5
|
fixed a bug in SDC generator for constraining SBs in tileable arch
|
2019-06-26 17:06:14 -06:00 |
|
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
|
tangxifan
|
7d85eb544d
|
start fixing bugs for SDC generator when using tileable arch
|
2019-06-26 16:48:17 -06:00 |
|
tangxifan
|
f5920c7422
|
fix bugs in ptc_num using for SB
|
2019-06-26 16:21:02 -06:00 |
|
tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
|
2019-06-26 15:51:11 -06:00 |
|
tangxifan
|
d2ed82d14d
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 15:00:39 -06:00 |
|
tangxifan
|
57616361c2
|
fixed critical bugs in cb configuration port indices
|
2019-06-26 14:58:52 -06:00 |
|
Baudouin Chauviere
|
d2bd2be76b
|
Warnings correction in the make sequence
|
2019-06-26 14:33:12 -06:00 |
|
Baudouin Chauviere
|
87ddca9f57
|
commiting current work. Stable but function not implemented yet
|
2019-06-26 14:22:02 -06:00 |
|
tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
|
2019-06-26 14:13:41 -06:00 |
|
tangxifan
|
9b6a4b39bb
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 11:36:08 -06:00 |
|
tangxifan
|
c879e7f6c5
|
fixed a critical bug when instanciating Connection blocks
|
2019-06-26 11:33:02 -06:00 |
|
Baudouin Chauviere
|
b7c2954b91
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-26 10:51:55 -06:00 |
|
Baudouin Chauviere
|
8f21a3b177
|
Memory leakage correction
|
2019-06-26 10:50:38 -06:00 |
|
tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
|
2019-06-26 10:50:23 -06:00 |
|
AurelienUoU
|
ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
|
tangxifan
|
a3670bb752
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-26 09:45:04 -06:00 |
|
Baudouin Chauviere
|
56557b94e7
|
Bug Fix
|
2019-06-26 08:53:46 -06:00 |
|
tangxifan
|
3c0ef2067d
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
|
Baudouin Chauviere
|
bb250ddef9
|
Bug fix in cpp
|
2019-06-25 16:47:10 -06:00 |
|
Ganesh Gore
|
6d3066174b
|
Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev
|
2019-06-25 15:12:13 -06:00 |