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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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tangxifan
2fbf9c2cfc
change to a higher simulation clock speed to accelerate CI verification.
...
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
tangxifan
130b78ca74
update arch in openfpga_flow
2020-04-11 18:00:37 -06:00
ganeshgore
eb3b02277a
Added XML and benchmarks for testing
2020-04-06 00:32:06 -06:00