Commit Graph

1494 Commits

Author SHA1 Message Date
tangxifan 03273371c0 [test] add a new test to validate local reset 2023-01-18 18:17:14 -08:00
tangxifan c9e00b7abc [arch] add a new example arch that supports local reset 2023-01-18 18:05:52 -08:00
tangxifan b6ae829518 [benchmark] add a new benchmark to validate dff 2023-01-18 17:59:52 -08:00
tangxifan 2c9593c1d4 [test] now use a new benchmark: discrete dffn to validate the clk gen locally feature 2023-01-15 13:09:40 -08:00
tangxifan 13aed6fff5 [test] still commment verification out 2023-01-15 12:17:59 -08:00
tangxifan 758cc7a089 [test] debugging 2023-01-15 11:44:48 -08:00
tangxifan 14bb76ec87 [test] remove verification steps for new test but leave a todo 2023-01-14 23:06:54 -08:00
tangxifan 297092f1fe [arch] now use a local clock as an input of a CLB 2023-01-14 22:12:00 -08:00
tangxifan 5aa85d82e6 [test] deploy the new test to basic regression tests 2023-01-13 22:07:45 -08:00
tangxifan 9222d085cd [test] now use local clock as one of the pins in a clock bus, but connected to global routing 2023-01-13 22:04:56 -08:00
tangxifan 26f71656de [test] update pin constraints 2023-01-13 21:12:18 -08:00
tangxifan 9e462d96e0 [arch] now use a dedicated input for locally generated clock signals 2023-01-13 20:46:04 -08:00
tangxifan 93107c752a [test] updating test case 2023-01-13 19:53:15 -08:00
tangxifan 1fb39f803b [doc] updated vpr arch naming rules 2023-01-13 19:52:58 -08:00
tangxifan a06ee30ca0 [arch] added a new vpr arch where clock can be generated by internal logics 2023-01-13 19:35:00 -08:00
tangxifan 1353577351 [test] added a new test to validate locally generated clocks 2023-01-13 16:45:30 -08:00
tangxifan 6400605603 [benchmark] add clock divider 2023-01-13 16:39:06 -08:00
tangxifan bbf83101be [test] deploy new test to ci 2023-01-11 17:11:28 -08:00
tangxifan c7dc3ce7dc [test] pass 2023-01-11 17:10:29 -08:00
tangxifan f6f153ace4 [test] debugging 2023-01-11 17:06:31 -08:00
tangxifan d5ebbeea9a [test] adding a new test to show how to automate generation of bus group files 2023-01-11 16:59:54 -08:00
tangxifan 54c3b965f2 [script] fixed a bug 2023-01-01 17:19:11 -08:00
tangxifan 3c8e157d7b [script] rename and fix typo 2023-01-01 17:13:23 -08:00
tangxifan 43cb498827 [test] deploy new tests to basic regression tests 2023-01-01 17:07:25 -08:00
tangxifan 83d7ff56e1 [script] add dedicated testcase for source commands 2023-01-01 17:04:24 -08:00
tangxifan cdec0cf28c [script] add a custom variable to specify the path to openfpga shell script 2023-01-01 16:51:21 -08:00
tangxifan c50daf273c [script] add example script for using source command 2023-01-01 16:50:10 -08:00
tangxifan d7a95a8ec2 [script] fixed some bugs 2022-12-30 18:30:52 -08:00
tangxifan 56a3e6e463 [test] reduce test size 2022-12-30 18:28:17 -08:00
tangxifan 93b020b0b3 [test] deploy new test to basic regression tests 2022-12-30 18:26:22 -08:00
tangxifan ae11a4fbf2 [test] add a new test case 2022-12-30 18:25:15 -08:00
tangxifan 6973e9fb98 [script] add an example script for vpr standalone calls 2022-12-30 18:23:14 -08:00
tangxifan c33b9f1b9b [script] enable eval mode in tcl reg test 2022-12-02 12:07:27 -08:00
tangxifan 156fac9fec [ci] deploy tcl test to ci 2022-12-02 11:46:14 -08:00
tangxifan 97c72c73f1 [test] add a small test to validate tcl integration 2022-12-02 11:43:46 -08:00
tangxifan 729a3a0249 [engine] tcl integration has initial success. Upload example scripts 2022-12-01 16:31:15 -08:00
tangxifan 9d8f4c1664 [script] format python codes 2022-11-21 14:21:31 -08:00
tangxifan 12d114bbae [test] hit the bug of tileable rr_graph skip it 2022-11-05 10:52:04 -07:00
tangxifan dc24e41c6b [test] relax minW for counter128, as VPR's router degrades in routability 2022-11-03 19:48:13 -07:00
tangxifan 513f7800aa [test] update golden outputs for no_cout_in_gsb testcase 2022-11-03 17:51:51 -07:00
tangxifan a88bc2d4de [test] update golden outputs for device4x4 2022-11-03 17:51:08 -07:00
tangxifan 5f74367c2e [test] update golden for device1x1 no time stamp netlists 2022-11-03 17:48:40 -07:00
tangxifan 958ef37a83
Merge pull request #864 from yunuseryilmaz18/master
Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
2022-10-30 12:16:21 -07:00
tangxifan 1abd6bca42
Merge branch 'master' into master 2022-10-27 10:18:59 -07:00
Yunus Emre ERYILMAZ 67a77d863e
Update dpram.v 2022-10-27 08:29:56 +03:00
Yunus Emre ERYILMAZ 0fe3bd36b6
Update dpram16k.v 2022-10-27 08:28:58 +03:00
Yunus Emre ERYILMAZ 74568b13a2
Update dpram1k.v 2022-10-26 16:32:14 +03:00
Yunus Emre ERYILMAZ 64b5b5c31c
Update dpram_2048x8.v 2022-10-26 16:31:16 +03:00
Yunus Emre ERYILMAZ f8b170ba75
Update dpram16k.v 2022-10-26 16:27:30 +03:00
Yunus Emre ERYILMAZ 82d8630ed4
Merge branch 'master' into patch-3 2022-10-24 13:32:42 +03:00