tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
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tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
|
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
|
2019-05-28 15:19:10 -06:00 |
Baudouin Chauviere
|
b48a27acf0
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-13 14:45:57 -06:00 |
|
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
|
2019-05-08 20:49:21 -06:00 |
|
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
|
Aur??Lien ALACCHI
|
0580d8243f
|
Add Autochek testbench option
|
2018-12-08 17:19:12 -07:00 |
|
Baudouin Chauviere
|
b6bb419e1d
|
add a ModelSim option
|
2018-12-06 14:13:37 -07:00 |
|
Aur??Lien ALACCHI
|
9a8c7b391a
|
Add process for modelsim script autogeneration
|
2018-12-05 09:20:47 -07:00 |
|
Aur??Lien ALACCHI
|
8ac566ecc0
|
Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
|
tangxifan
|
c67ba5f58a
|
clean up codes
|
2018-09-27 14:26:08 -06:00 |
|
tangxifan
|
d683134b12
|
rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |