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riscv
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OpenFPGA
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tangxifan
47cb1cc2d4
[Test] Deploy synthesizable verilog test to CI
2021-02-17 16:13:15 -07:00
tangxifan
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00