Tarachand Pagarani
|
426b6449d8
|
change the test to turn off power analysis
|
2021-02-15 02:45:38 -08:00 |
tangxifan
|
8853370c60
|
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
|
2021-02-04 20:20:10 -07:00 |
|
tangxifan
|
d3397f6936
|
[Script] Remove activity from bitstream setting example script
|
2021-02-02 09:25:36 -07:00 |
|
tangxifan
|
7f14dfbe87
|
[Script] Add example script to use bitstream setting
|
2021-02-02 09:18:08 -07:00 |
|
tangxifan
|
8b74947737
|
[Script] Now multi-clock openfpga shell script no longer needs activity file
|
2021-01-29 11:40:33 -07:00 |
|
tangxifan
|
3fdd5ae8b3
|
[Script] Use pin constraints in template script
|
2021-01-19 17:42:25 -07:00 |
|
tangxifan
|
12e0efd03e
|
[Script] Add an example openfpga script to use repack design constraints
|
2021-01-17 10:33:56 -07:00 |
|
tangxifan
|
c5a2027f36
|
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
|
2021-01-13 15:41:48 -07:00 |
|
tangxifan
|
18d2a8ce19
|
[Flow] Add new script for fixed device layout using global tile clock
|
2021-01-10 11:08:02 -07:00 |
Lalit Sharma
|
2484721a45
|
Updating write_verilog_testbench by removing option explicit_port_mapping
|
2020-12-22 22:17:50 -08:00 |
|
tangxifan
|
fd80cacaa3
|
[Flow] Add example script for behaviorial verilog generation
|
2020-11-22 21:14:10 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |