tangxifan
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b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |
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tangxifan
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faabdab815
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[Tool] Remove redundant tab in bitstream setting writer
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2021-02-01 18:04:21 -07:00 |
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tangxifan
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d5b1cc5ec7
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[Tool] Bug fix in parser for bitstream settings
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2021-02-01 18:01:42 -07:00 |
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tangxifan
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f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
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3b7762ef85
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[Lib] Now try to call undefined command will cause a error code to return
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2021-01-24 17:44:51 -07:00 |
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tangxifan
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a8158322ef
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[Tool] Bug fix in setting command execution status in OpenFPGA shell
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2021-01-24 17:25:03 -07:00 |
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tangxifan
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fd0e73a9bb
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[Tool] Enhance return code for openfpga shell
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2021-01-24 14:48:27 -07:00 |
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tangxifan
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8cac3291cb
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[Tool] Add batch mode to openfpga shell execution
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2021-01-24 14:33:58 -07:00 |
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tangxifan
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4cc8b08a6c
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[Tool] Add openfpga version display
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2021-01-23 16:38:00 -07:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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ecd955124b
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[Lib] Add libpcf to CMakelist and bug fix
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2021-01-19 15:51:14 -07:00 |
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tangxifan
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52ac7826eb
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[Lib] Add a library of parser/writer for pin constraint file (PCF)
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2021-01-19 15:45:45 -07:00 |
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tangxifan
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ea9d6bfe91
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[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
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113119bd8e
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[Lib] Fix the bug in repack design constraint parser
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2021-01-17 10:39:55 -07:00 |
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tangxifan
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2efe513122
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[Tool] Now repack consider design constraints; test pending
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2021-01-16 21:57:17 -07:00 |
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tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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b86adabe69
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[Lib] Remove unused data storage from repack design constraints
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2021-01-16 21:14:52 -07:00 |
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tangxifan
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706e84bb62
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[Lib] Bug fix in testing program
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2021-01-16 18:15:56 -07:00 |
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tangxifan
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67c54c4d3b
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[Lib] Bug fix in the repack design constraint lib
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2021-01-16 17:34:22 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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9d80f1ab39
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[Lib] Add test program to the library of repack design constraints
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2021-01-16 17:18:42 -07:00 |
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tangxifan
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03b5bcc244
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[Lib] Add XML writer for repack design constraints
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2021-01-16 17:15:31 -07:00 |
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tangxifan
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2a7601fb7e
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[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
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2021-01-16 17:14:51 -07:00 |
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tangxifan
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f1bfa2ef8c
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[Lib] Add XML parser for repack design constraints
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2021-01-16 17:03:01 -07:00 |
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tangxifan
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8be12b6e82
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[Lib] Add example design constraint file
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2021-01-16 16:36:10 -07:00 |
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tangxifan
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a926c74ae5
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[Lib] Add CMake script to compile the repack design constraint library
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2021-01-16 16:35:46 -07:00 |
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tangxifan
|
b57dc7b898
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[Lib] Add repack design constraint library
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2021-01-16 16:35:13 -07:00 |
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tangxifan
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b8e4675a3a
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[Tool] Add missing file
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2021-01-15 14:48:19 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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4124777948
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[Tool] Set (x,y) to be optional XML syntax in tile annotation
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2021-01-09 18:56:41 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
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cb34be0dc0
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[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
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2021-01-04 15:13:54 -07:00 |
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tangxifan
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d195b9e32c
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[Tool] Bug fix in XML syntax to define default values for a global tile port
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2020-12-02 17:03:48 -07:00 |
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tangxifan
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e959821813
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[Tool] Enhance internal check functions for tile annotation
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2020-11-11 13:59:24 -07:00 |
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tangxifan
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4dc0fb81c5
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[Tool] Bug fix for clang compilation error
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2020-11-10 20:32:58 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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67af145455
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[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
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tangxifan
|
6fbdbe68ae
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[Tool] Add tile annotation parser
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2020-11-10 14:32:24 -07:00 |
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tangxifan
|
0a273ffab6
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
|
e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
|
1e70825383
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[OpenFPGA Tool] Add XML syntax for configurable regions
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2020-09-28 13:51:43 -06:00 |
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tangxifan
|
052b8b71c7
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[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
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2020-09-27 20:54:58 -06:00 |
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tangxifan
|
491433fae2
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[OpenFPGA Tool] Update XML parser for fabric regions
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2020-09-27 20:41:01 -06:00 |
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tangxifan
|
48b2bff0d9
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[OpenFPGA Tool] Update fabric key data structure to support regions
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2020-09-27 20:08:11 -06:00 |