Ganesh Gore
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66bb8a5e4b
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Updated RRAM architecture file
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2019-08-17 02:20:04 -06:00 |
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Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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Ganesh Gore
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c43c3cdf25
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Added VPR output parse option
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2019-08-16 13:36:39 -06:00 |
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Ganesh Gore
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effbd332aa
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Added task report generation
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2019-08-16 10:59:44 -06:00 |
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Ganesh Gore
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901932a4fc
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First draft: Working openfpga task flow
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2019-08-16 09:44:50 -06:00 |
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Ganesh Gore
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5d3708651e
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Added fpga_flow and fpga_task script
+ Missed local intermediate commits
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2019-08-15 14:39:58 -06:00 |
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Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |