tangxifan
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637dd08bea
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[test] fixed a bug
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2024-11-26 18:09:39 -08:00 |
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tangxifan
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a1a5f8cfb6
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[test] add new test to valid force clock tap mux routing
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2024-11-26 17:36:02 -08:00 |
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tangxifan
|
d71e7f7412
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[test] add new test to validate default mode bit overwrite
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2024-11-25 16:06:40 -08:00 |
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tangxifan
|
d264b39dab
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[test] update golden
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2024-11-13 20:13:02 -08:00 |
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tangxifan
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e863333f22
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[test] relax route W to bypass VPR bugs
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2024-11-13 19:01:55 -08:00 |
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tangxifan
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9e6f9759d7
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[test] fixed the bugs in unicode failures. Refer to ttps://github.com/davidbombal/red-python-scripts/issues/4
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2024-11-13 12:27:33 -08:00 |
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tangxifan
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5c8b7c565c
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[test] clean up python deprecation notice
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2024-11-13 12:07:14 -08:00 |
Lin
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3c219967df
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add testcase
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2024-11-01 12:15:08 +08:00 |
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tangxifan
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c41c142331
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[test] update golden
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2024-10-17 17:01:05 -07:00 |
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tangxifan
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b6b75fd19c
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[test] bypass vtr bugs
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2024-10-17 14:58:56 -07:00 |
|
Lin
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fc5c0f6965
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modified testcases
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2024-10-09 17:41:01 +08:00 |
|
Lin
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88e12a0afa
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modified test cases & xsd file
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2024-10-09 17:21:49 +08:00 |
Jingrong Lin
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be3546f7e3
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Merge branch 'master' into bin_format
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2024-10-08 13:28:53 +08:00 |
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tangxifan
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aa86381d65
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[test] adjust route chan width to avoid vpr bug on min route chan width (some case failed)
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2024-10-07 17:17:36 -07:00 |
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tangxifan
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efdb8bf441
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[test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition
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2024-10-07 17:14:11 -07:00 |
|
Lin
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20238c1a2d
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modified testcase
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2024-09-29 12:30:39 +08:00 |
|
Lin
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6864159f31
|
modified testcases
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2024-09-29 11:20:46 +08:00 |
|
Lin
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87ca9f3006
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add three testcases to test bin read and write
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2024-09-29 11:09:01 +08:00 |
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tangxifan
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33a253da3d
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[core] fixed the bug
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2024-09-20 22:20:41 -07:00 |
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tangxifan
|
6551ca81e5
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[core] debugging
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2024-09-20 19:48:02 -07:00 |
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tangxifan
|
6d3d36626e
|
[test] typo
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2024-09-20 19:29:47 -07:00 |
|
tangxifan
|
ed33b62a60
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[test] add new tests to validate intermediate drivers in clock
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2024-09-20 19:27:40 -07:00 |
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tangxifan
|
7b4f06ed7d
|
[test] validate mux2 at last stage
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2024-09-18 17:40:13 -07:00 |
|
Jingrong Lin
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77b188060b
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Merge branch 'master' into preloading_clean
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2024-09-11 11:08:49 +08:00 |
victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
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tangxifan
|
f912af513b
|
[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
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2024-09-09 13:54:20 -07:00 |
Victor
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8d97ebd980
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Add more test cases and update documentation about the YAML file format of this command
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2024-09-09 17:49:10 +08:00 |
|
Lin
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d15025d9d2
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add a task case to ease the use of compress_routing option
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2024-09-09 14:18:47 +08:00 |
|
Victor
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83fc1210b5
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add test case of report_reference to basic_reg_test.sh
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2024-09-06 18:28:23 +08:00 |
|
Victor
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9a2fc86dcd
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add dependency on build_fabric
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2024-09-06 17:58:47 +08:00 |
|
Victor
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7bacc781d0
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update code according to code review comments
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2024-09-06 15:39:08 +08:00 |
|
Lin
|
1d35a17a8b
|
delete redundant file
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2024-08-30 14:18:59 +08:00 |
|
Lin
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acce64058c
|
add test case
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2024-08-30 14:17:42 +08:00 |
|
Lin
|
8372eead6a
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add preload flag to device_rr_gsb and revert change to build fabric
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2024-08-28 18:14:33 +08:00 |
|
Lin
|
5153cee4dd
|
mod reg_test script
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2024-08-26 02:47:13 -07:00 |
|
Lin
|
701a7a5c52
|
add test case
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2024-08-26 02:45:57 -07:00 |
|
Lin
|
88fa9f8d39
|
add test case
|
2024-08-25 23:41:19 -07:00 |
|
tangxifan
|
05ef972911
|
[test] typo
|
2024-08-15 15:36:08 -07:00 |
|
tangxifan
|
2c35840457
|
[test] add a new test to validate CHANY clock spin in DEC
|
2024-08-15 14:24:31 -07:00 |
|
tangxifan
|
586dd1a510
|
[test] add a new and strong test to validate the disable unused clock spines
|
2024-08-15 10:24:58 -07:00 |
|
tangxifan
|
84cc7090ce
|
[test] add a new test to validate that pb pin fixup impacts global net now
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2024-08-14 10:37:46 -07:00 |
|
tangxifan
|
542571ce89
|
[test] code format
|
2024-08-09 18:20:27 -07:00 |
|
tangxifan
|
c6246ae905
|
[test] typo
|
2024-08-09 17:10:51 -07:00 |
|
tangxifan
|
a05bfb55dd
|
[test] typo
|
2024-08-09 17:05:48 -07:00 |
|
tangxifan
|
38f1bdba4e
|
[test] add a new test case
|
2024-08-09 17:04:10 -07:00 |
|
tangxifan
|
602ab72002
|
[test] add associated openfpga arch
|
2024-08-09 17:01:23 -07:00 |
|
tangxifan
|
e6c508f081
|
[test] add a new arch to validate that clock network tap supports subtiles
|
2024-08-09 16:51:34 -07:00 |
|
tangxifan
|
1026df4890
|
[test] add new tests to validate the options for undriven inputs in verilog netlists
|
2024-08-06 20:58:00 -07:00 |
|
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
|
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |