Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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e6cc3c4942
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
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tangxifan
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ec184ef532
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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
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2021-10-30 14:46:12 -07:00 |
Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |