Aur??Lien ALACCHI
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3ef0047f3e
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Add disclaimer in architecture file
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2021-01-29 09:22:23 -07:00 |
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Aur??Lien ALACCHI
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f50d033037
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Repair format (tab and space mismatched)
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2021-01-28 10:26:04 -07:00 |
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Aur??Lien ALACCHI
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f3b081c6d4
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Add task for lutram
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2021-01-27 15:57:58 -07:00 |
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Aur??Lien ALACCHI
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3e0944bee8
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Add required files for LUTRAM integration and testing
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2021-01-27 14:56:41 -07:00 |
Ganesh Gore
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0b82b6439b
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[Regression] Upgraded runtime enviroment to python3.8
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2021-01-26 16:40:45 -07:00 |
tangxifan
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af0646260c
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[Test] Bug fix in pin constraints
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2021-01-19 17:44:05 -07:00 |
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tangxifan
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186f2f1968
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[Test] Use pin constraint in multi-clock test case
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2021-01-19 17:42:40 -07:00 |
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tangxifan
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3fdd5ae8b3
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[Script] Use pin constraints in template script
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2021-01-19 17:42:25 -07:00 |
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tangxifan
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e17a5cbbf2
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[Test] Rename to pin constraint to comply with libpcf requirement
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2021-01-19 15:52:51 -07:00 |
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tangxifan
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ab25e1af5f
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[Test] Add example XML for net mapping between benchmark to FPGA
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2021-01-19 09:29:21 -07:00 |
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tangxifan
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ea9d6bfe91
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[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
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dd74f05a31
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[Test] Add repack constraints to tests
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2021-01-17 10:35:36 -07:00 |
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tangxifan
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12e0efd03e
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[Script] Add an example openfpga script to use repack design constraints
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2021-01-17 10:33:56 -07:00 |
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tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |
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tangxifan
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9154cfdeec
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[Flow] Add comments for the design constraint file
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2021-01-16 15:34:01 -07:00 |
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tangxifan
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6ab0f71896
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[Test] Add an example of repack pin constraints file
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2021-01-16 14:38:39 -07:00 |
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tangxifan
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89f9d24d32
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[Flow] Update simulation settings for multiple clock to allow unique clock port name
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2021-01-15 10:35:43 -07:00 |
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tangxifan
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dbed04b53b
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[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
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2021-01-14 15:42:21 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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923f3a3401
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[Flow] Add an example simulation settings for a 4-clock FPGA fabric
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2021-01-13 17:29:39 -07:00 |
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tangxifan
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9a906e787b
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[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
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2021-01-13 15:43:31 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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c5a2027f36
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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tangxifan
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7af6d7f07d
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[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
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2021-01-13 15:38:44 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
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ccf3e037ff
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[Benchmark] Change multi-clock counter from 8-bit to 4-bit
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2021-01-13 13:31:06 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
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2f1aceda67
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[Doc] Update documentation about architecture naming rules
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2021-01-12 18:01:24 -07:00 |
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tangxifan
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9fa49c401c
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[Arch] Add openfpga architecture which uses 4 global clocks
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2021-01-12 18:00:22 -07:00 |
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tangxifan
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16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
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tangxifan
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7ccdff4543
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[Arch] Add an architecture using 4 clocks
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2021-01-12 17:55:57 -07:00 |
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tangxifan
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3790f2c26a
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[Benchmark] Add 2-clock micro benchmark
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2021-01-12 17:48:52 -07:00 |
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tangxifan
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a0b9f2b40d
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Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
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2021-01-11 10:02:31 -07:00 |
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tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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tangxifan
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18d2a8ce19
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
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tangxifan
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aaf582acc5
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[Arch] Bug fix
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2021-01-10 11:05:57 -07:00 |
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tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
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tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
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tangxifan
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dfb3e32147
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[Arch] Add openfpga archiecture for registerable I/O
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2021-01-10 10:54:41 -07:00 |
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tangxifan
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853e7b1a40
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[Arch] Add vpr architecture where I/O can be either combinational or registered
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2021-01-10 10:54:09 -07:00 |
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tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
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tangxifan
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6521aa2e7a
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[Benchmark] Bug fix in pipelined and2 benchmark
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2021-01-10 10:27:59 -07:00 |
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tangxifan
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4412bbd084
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[Benchmark] Add a micro benchmark to test pipelined architecture
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2021-01-10 10:21:30 -07:00 |
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tangxifan
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0b74575606
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[Arch] Update arch using global reset tile port
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2021-01-09 18:04:55 -07:00 |
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tangxifan
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7b24da267a
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[Arch] Remove port size XML syntax
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2021-01-09 16:30:46 -07:00 |
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tangxifan
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9f12b25a24
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[Arch] Add port size to global port defined thru tile annotation
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2021-01-09 16:23:28 -07:00 |
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tangxifan
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0f5f0a3527
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[Arch] Add x,y coordinates to global port definition
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2021-01-09 15:50:09 -07:00 |
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tangxifan
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a14a56772a
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[Arch] Introduce new XML syntax for global port in tile annotation
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2021-01-09 15:48:42 -07:00 |