Commit Graph

31 Commits

Author SHA1 Message Date
nadeemyaseen-rs 27d280a070 added in CMakeList.txt to check if yosys binary already exist to avoid the re-compilation of yosys 2021-11-29 18:33:13 +05:00
coolbreeze413 264023c2c9 remove clean step in compilation of yosys/plugins to check CI 2021-11-15 21:41:17 +05:30
Lalit Sharma fe74c42252 Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 01:46:06 -08:00
coolbreeze413 a823c3e143 remove clean step in build to avoid long compilation times 2021-11-04 10:19:25 +05:30
coolbreeze413 3fa373f8bc add plugins, set yosys install for plugin 2021-11-04 07:22:09 +05:30
tangxifan 33c12c8f0e
Update CMakeLists.txt 2021-04-26 20:51:54 -06:00
Lalit Sharma b621c4f694 Removing yosys-symbiflow-plugins compilation from CMakefile 2020-12-10 21:44:57 -08:00
Lalit Sharma 07dfd35e12 Adding yosys-symbiflow-plugins as submodule and adding tcllib as dependency in CI 2020-12-08 20:35:57 -08:00
Lalit Sharma 8a2681f99f Re-setting option YOSYS_ENABLE_TCL to ON, as yosys compilation depends on tcl 2020-12-08 09:21:25 -08:00
Lalit Sharma d7ec481e9e Adding updates to checkout submodules 2020-12-08 08:52:35 -08:00
Lalit Sharma ed9535693c Updating CMakeList.txt to compile yosys 2020-12-08 01:29:36 -08:00
tangxifan 4f8260a7ba remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
tangxifan dfdfea2081 fix the bug in CMake Script due to splitted simulation setting files 2020-06-11 19:31:15 -06:00
tangxifan 46b53f20ba add ezgl support in the CMakelist for VPR8 2020-01-27 13:44:28 -07:00
tangxifan 523f9ac391 start implement openfpga shell and use vpr as a macro 2020-01-22 20:20:10 -07:00
tangxifan db503ffebf add openfpga read xml executable and start min unit test 2020-01-13 21:05:58 -07:00
tangxifan 48ecb6e48b immigrate XML parser for circuit_lib to library readarchopenfpga 2020-01-12 18:11:00 -07:00
tangxifan 0740684567 remove libs from cache list 2020-01-03 22:06:40 -05:00
tangxifan b728773159 add vtr assert level and copy missing cmake modules from vtr project 2020-01-03 21:56:15 -05:00
tangxifan 670642ee42 add executable to vpr8 directory 2020-01-03 16:50:29 -07:00
tangxifan 0f012a32a5 add vpr8 to cmake compilation 2020-01-03 16:45:31 -07:00
tangxifan f1bafffa87 add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
tangxifan e9ed64c926 try to let cmake identify libini 2019-11-01 21:17:35 -06:00
tangxifan 5e156dc725 minor fix for OSX and update travis using ccache to speed up compilation 2019-08-21 15:25:36 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
AurelienUoU f940c4fd59 Third try to fix issues with graphics on mac 2019-05-15 13:22:14 -06:00
AurelienUoU 41dc359b50 Remove graphics on MacOS -> X11 deprecated and cannot be found by travis 2019-05-15 10:39:20 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
tangxifan 6e6ae1cc3d fixed bugs in CMakeLists.txt and Makefile 2019-05-03 23:03:04 -06:00
tangxifan e5a18b7cca Add CMakeSupport, TODO: create CMAKE support for yosys 2019-05-03 19:04:02 -06:00