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Merge pull request #34 from LNIS-Projects/dev 

Dev
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS) 2019-12-04 19:26:14 -07:00 committed by GitHub
parent c091b5ea99 a04631305c
commit ffe90b1da6
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GPG Key ID: 4AEE18F83AFDEB23
20 changed files with 112 additions and 3976 deletions
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1
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
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@ -27,7 +27,6 @@
/* Header files for Verilog generator */
#include "verilog_global.h"
#include "verilog_utils.h"
#include "build_grid_modules.h"
/********************************************************************

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
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@ -162,6 +162,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
* See more details in the function print_verilog_mux_local_decoder() for more details
***************************************************************************************/
void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -222,8 +223,9 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
/* Close the file stream */
fp.close();
/* Add fname to the linked list when debugging is finished */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}
/***************************************************************************************

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h
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@ -9,13 +9,16 @@
/* Include other header files which are dependency on the function declared below */
#include <fstream>
#include <string>
#include <vector>
#include "vpr_types.h"
#include "circuit_library.h"
#include "mux_graph.h"
#include "mux_library.h"
#include "module_manager.h"
void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp
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@ -525,6 +525,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
* etc.
***********************************************/
void print_verilog_submodule_essentials(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib) {
@ -575,8 +576,6 @@ void print_verilog_submodule_essentials(ModuleManager& module_manager,
/* Close file handler*/
fp.close();
/* Add fname to the linked list */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
return;
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h
View File

@ -13,6 +13,7 @@
#include "circuit_library.h"
void print_verilog_submodule_essentials(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib);

19
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
View File

@ -26,7 +26,6 @@
/* Header files for Verilog generator */
#include "verilog_global.h"
#include "verilog_utils.h"
#include "verilog_writer_utils.h"
#include "verilog_module_writer.h"
#include "verilog_grid.h"
@ -183,6 +182,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp,
*****************************************************************************/
static
void print_verilog_grid(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& subckt_dir,
t_type_ptr phy_block_type,
@ -261,8 +261,8 @@ void print_verilog_grid(ModuleManager& module_manager,
/* Close file handler */
fp.close();
/* Add fname to the linked list */
grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}
/*****************************************************************************
@ -275,6 +275,9 @@ void print_verilog_grids(ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_mapping) {
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
/* Enumerate the types, dump one Verilog module for each */
for (int itype = 0; itype < num_types; itype++) {
if (EMPTY_TYPE == &type_descriptors[itype]) {
@ -284,7 +287,7 @@ void print_verilog_grids(ModuleManager& module_manager,
/* Special for I/O block, generate one module for each border side */
for (int iside = 0; iside < NUM_SIDES; iside++) {
Side side_manager(iside);
print_verilog_grid(module_manager,
print_verilog_grid(module_manager, netlist_names,
verilog_dir, subckt_dir,
&type_descriptors[itype],
side_manager.get_side(),
@ -293,7 +296,7 @@ void print_verilog_grids(ModuleManager& module_manager,
continue;
} else if (FILL_TYPE == &type_descriptors[itype]) {
/* For CLB */
print_verilog_grid(module_manager,
print_verilog_grid(module_manager, netlist_names,
verilog_dir, subckt_dir,
&type_descriptors[itype],
NUM_SIDES,
@ -301,7 +304,7 @@ void print_verilog_grids(ModuleManager& module_manager,
continue;
} else {
/* For heterogenenous blocks */
print_verilog_grid(module_manager,
print_verilog_grid(module_manager, netlist_names,
verilog_dir, subckt_dir,
&type_descriptors[itype],
NUM_SIDES,
@ -312,9 +315,7 @@ void print_verilog_grids(ModuleManager& module_manager,
/* Output a header file for all the logic blocks */
vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n");
std::string grid_verilog_fname(logic_block_verilog_file_name);
/* TODO: remove .bak when it is ready */
//grid_verilog_fname += ".bak";
dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head,
print_verilog_netlist_include_header_file(netlist_names,
subckt_dir.c_str(),
grid_verilog_fname.c_str());
}

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp
View File

@ -29,13 +29,12 @@
* in the circuit library
********************************************************************/
void print_verilog_submodule_luts(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
/* TODO: remove .bak when this part is completed and tested */
std::string verilog_fname = submodule_dir + luts_verilog_file_name;
//verilog_fname +=".bak";
std::fstream fp;
@ -70,7 +69,7 @@ void print_verilog_submodule_luts(ModuleManager& module_manager,
/* Close the file handler */
fp.close();
/* Add fname to the linked list */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h
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@ -13,6 +13,7 @@
#include "module_manager.h"
void print_verilog_submodule_luts(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp
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@ -97,6 +97,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager,
* memory-bank organization for the memories.
********************************************************************/
void print_verilog_submodule_memories(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -104,7 +105,6 @@ void print_verilog_submodule_memories(ModuleManager& module_manager,
const bool& use_explicit_port_map) {
/* Plug in with the mux subckt */
std::string verilog_fname(submodule_dir + memories_verilog_file_name);
//verilog_fname += ".bak";
/* Create the file stream */
std::fstream fp;
@ -187,7 +187,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager,
/* Close the file stream */
fp.close();
/* Add fname to the linked list */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h
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@ -14,6 +14,7 @@
#include "module_manager.h"
void print_verilog_submodule_memories(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp
View File

@ -1218,6 +1218,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
* multiplexers in the FPGA device
**********************************************/
void print_verilog_submodule_muxes(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
t_sram_orgz_info* cur_sram_orgz_info,
@ -1279,7 +1280,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info,
mux_lib.max_mux_size(), mux_lib.max_mux_size());
/* Add fname to the linked list when debugging is finished */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h
View File

@ -7,6 +7,7 @@
/* Include other header files which are dependency on the function declared below */
#include <fstream>
#include <vector>
#include "circuit_library.h"
#include "mux_graph.h"
@ -14,6 +15,7 @@
#include "module_manager.h"
void print_verilog_submodule_muxes(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
t_sram_orgz_info* cur_sram_orgz_info,

40
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp
View File

@ -11,7 +11,6 @@
/* Include FPGA-Verilog header files*/
#include "verilog_global.h"
#include "verilog_utils.h"
#include "verilog_writer_utils.h"
#include "verilog_module_writer.h"
#include "verilog_routing.h"
@ -72,6 +71,7 @@
********************************************************************/
static
void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
@ -107,8 +107,8 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma
/* Close file handler */
fp.close();
/* Add fname to the linked list */
routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}
/*********************************************************************
@ -176,6 +176,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma
********************************************************************/
static
void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
@ -207,19 +208,17 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
/* Close file handler */
fp.close();
/* Add fname to the linked list */
routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str());
return;
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}
/********************************************************************
* Iterate over all the connection blocks in a device
* and build a module for each of them
*******************************************************************/
static
void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const DeviceRRGSB& L_device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
@ -239,7 +238,7 @@ void print_verilog_flatten_connection_block_modules(ModuleManager& module_manage
|| (true != rr_gsb.is_cb_exist(cb_type))) {
continue;
}
print_verilog_routing_connection_box_unique_module(module_manager,
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
verilog_dir,
subckt_dir,
rr_gsb, cb_type,
@ -266,6 +265,9 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
/* We only support uni-directional routing architecture now */
VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
/* TODO: deprecate DeviceCoordinator, use vtr::Point<size_t> only! */
DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range();
@ -273,7 +275,7 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
print_verilog_routing_switch_box_unique_module(module_manager,
print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
verilog_dir,
subckt_dir,
rr_gsb,
@ -281,12 +283,12 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
}
}
print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
print_verilog_netlist_include_header_file(netlist_names,
subckt_dir.c_str(),
routing_verilog_file_name);
}
@ -311,10 +313,13 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager,
/* We only support uni-directional routing architecture now */
VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality);
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
/* Build unique switch block modules */
for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb);
print_verilog_routing_switch_box_unique_module(module_manager,
print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
verilog_dir,
subckt_dir,
unique_mirror,
@ -325,7 +330,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager,
for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb);
print_verilog_routing_connection_box_unique_module(module_manager,
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
verilog_dir,
subckt_dir,
unique_mirror, CHANX,
@ -336,7 +341,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager,
for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb);
print_verilog_routing_connection_box_unique_module(module_manager,
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
verilog_dir,
subckt_dir,
unique_mirror, CHANY,
@ -344,8 +349,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager,
}
vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n");
dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head,
print_verilog_netlist_include_header_file(netlist_names,
subckt_dir.c_str(),
routing_verilog_file_name);
}

23
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp
View File

@ -8,8 +8,6 @@
#include "util.h"
/* FPGA-Verilog header files */
#include "verilog_global.h"
#include "verilog_utils.h"
#include "verilog_submodule_utils.h"
#include "verilog_essential_gates.h"
#include "verilog_decoders.h"
@ -17,6 +15,7 @@
#include "verilog_lut.h"
#include "verilog_wire.h"
#include "verilog_memory.h"
#include "verilog_writer_utils.h"
/* Header file for this source file */
#include "verilog_submodules.h"
@ -45,9 +44,13 @@ void print_verilog_submodules(ModuleManager& module_manager,
vpr_printf(TIO_MESSAGE_INFO,
"Registering user-defined modules...\n");
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib);
print_verilog_submodule_essentials(module_manager,
netlist_names,
std::string(verilog_dir),
std::string(submodule_dir),
Arch.spice->circuit_lib);
@ -59,9 +62,10 @@ void print_verilog_submodules(ModuleManager& module_manager,
/* NOTE: local decoders generation must go before the MUX generation!!!
* because local decoders modules will be instanciated in the MUX modules
*/
print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib,
print_verilog_submodule_mux_local_decoders(module_manager, netlist_names,
mux_lib, Arch.spice->circuit_lib,
std::string(verilog_dir), std::string(submodule_dir));
print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info,
print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info,
std::string(verilog_dir), std::string(submodule_dir),
fpga_verilog_opts.dump_explicit_verilog);
@ -69,16 +73,17 @@ void print_verilog_submodules(ModuleManager& module_manager,
/* LUTes */
vpr_printf(TIO_MESSAGE_INFO,
"Generating modules for LUTs...\n");
print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir),
print_verilog_submodule_luts(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir),
fpga_verilog_opts.dump_explicit_verilog);
/* Hard wires */
print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
print_verilog_submodule_wires(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
/* 4. Memories */
vpr_printf(TIO_MESSAGE_INFO,
"Generating modules for configuration memory blocks...\n");
print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib,
print_verilog_submodule_memories(module_manager, netlist_names,
mux_lib, Arch.spice->circuit_lib,
std::string(verilog_dir), std::string(submodule_dir),
fpga_verilog_opts.dump_explicit_verilog);
@ -89,8 +94,8 @@ void print_verilog_submodules(ModuleManager& module_manager,
/* Create a header file to include all the subckts */
vpr_printf(TIO_MESSAGE_INFO,
"Generating header file for basic submodules...\n");
dump_verilog_subckt_header_file(submodule_verilog_subckt_file_path_head,
"Generating header file for primitive modules...\n");
print_verilog_netlist_include_header_file(netlist_names,
submodule_dir,
submodule_verilog_file_name);
}

3615
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
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File diff suppressed because it is too large Load Diff

299
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
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@ -1,299 +0,0 @@
#ifndef VERILOG_UTILS_H
#define VERILOG_UTILS_H
#include "vpr_types.h"
void init_list_include_verilog_netlists(t_spice* spice);
void init_include_user_defined_verilog_netlists(t_spice spice);
void dump_include_user_defined_verilog_netlists(FILE* fp,
t_spice spice);
void dump_verilog_file_header(FILE* fp,
char* usage);
void dump_verilog_preproc(FILE* fp,
t_syn_verilog_opts fpga_verilog_opts,
enum e_verilog_tb_type verilog_tb_type);
void verilog_include_defines_preproc_file(FILE* fp,
char* formatted_verilog_dir);
FILE* verilog_create_one_subckt_file(char* subckt_dir,
const char* subckt_name_prefix,
const char* verilog_subckt_file_name_prefix,
char** verilog_fname);
FILE* verilog_create_one_subckt_file(char* subckt_dir,
const char* subckt_name_prefix,
const char* verilog_subckt_file_name_prefix,
int grid_x, int grid_y,
char** verilog_fname);
void dump_verilog_subckt_header_file(t_llist* subckt_llist_head,
const char* subckt_dir,
const char* header_file_name);
char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_generic_port(FILE* fp,
enum e_dump_verilog_port_type dump_port_type,
char* port_name, int port_lsb, int port_msb);
void dump_verilog_generic_port_no_repeat(FILE* fp,
enum e_dump_verilog_port_type dump_port_type,
char* port_name, int port_lsb, int port_msb);
char* chomp_verilog_prefix(char* verilog_node_prefix);
char* format_verilog_node_prefix(char* verilog_node_prefix);
char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type);
int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map);
int rec_dump_verilog_spice_model_global_ports(FILE* fp,
const t_spice_model* cur_spice_model,
boolean dump_port_type,
boolean recursive,
boolean require_explicit_port_map,
boolean is_lib_name);
int dump_verilog_global_ports(FILE* fp, t_llist* head,
boolean dump_port_type,
bool is_explicit_mapping);
int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head,
boolean dump_port_type);
void dump_verilog_mux_sram_one_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_mux_spice_model, int mux_size,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_sram_one_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_mux_sram_one_local_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_mux_spice_model, int mux_size,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_local_outport(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_sram_outports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_formal_verification_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_one_port(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_sram_local_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_reserved_sram_one_port(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
int port_type_index,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb);
void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_mux_spice_model, int mux_size,
int sram_lsb, int sram_msb);
void dump_verilog_reserved_sram_ports(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
int sram_lsb, int sram_msb,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_mux_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model);
void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* sram_verilog_model);
void dump_verilog_ccff_config_bus(FILE* fp,
t_spice_model* mem_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type);
void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int cur_num_sram,
int num_mem_reserved_conf_bits,
int num_mem_conf_bits);
void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits);
void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits);
void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
bool is_explicit_mapping);
void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
t_sram_orgz_info* cur_sram_orgz_info,
int mux_size, int cur_num_sram,
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
bool is_explicit_mapping);
void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
char* general_port_prefix, int lsb, int msb,
enum e_dump_verilog_port_type dump_port_type,
bool is_explicit_mapping);
void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
int lsb, int msb);
void dump_verilog_toplevel_one_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
int pin_index, int side,
int x, int y,
boolean dump_port_type);
char* generate_verilog_subckt_name(t_spice_model* spice_model,
char* postfix);
char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
t_spice_model* mem_model,
char* postfix);
char* generate_verilog_decoder_subckt_name(int addr_len, int data_len);
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix);
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix);
enum e_dump_verilog_port_type
convert_spice_model_port_type_to_verilog_port_type(enum e_spice_model_port_type spice_model_port_type);
int dump_verilog_mem_module_one_port_map(FILE* fp,
t_spice_model* mem_model,
enum e_spice_model_port_type port_type_to_dump,
boolean dump_port_type,
int index, int num_mem, boolean dump_first_comma,
boolean require_explicit_port_map);
void dump_verilog_mem_module_port_map(FILE* fp,
t_spice_model* mem_model,
boolean dump_port_type,
int lsb, int num_mem,
boolean require_explicit_port_map);
void dump_verilog_mem_sram_submodule(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info,
t_spice_model* cur_verilog_model, int mux_size,
t_spice_model* cur_sram_verilog_model,
int lsb, int msb,
bool is_explicit_mapping);
char* gen_verilog_grid_one_pin_name(int x, int y,
int height, int side, int pin_index,
boolean for_top_netlist);
char* gen_verilog_routing_channel_one_pin_name(t_rr_node* chan_rr_node,
int x, int y, int track_idx,
enum PORTS pin_direction);
char* gen_verilog_routing_channel_one_midout_name(t_cb* cur_cb_info,
int track_idx);
char* gen_verilog_one_cb_module_name(t_cb* cur_cb_info);
char* gen_verilog_one_cb_instance_name(t_cb* cur_cb_info);
char* gen_verilog_one_sb_module_name(t_sb* cur_sb_info);
char* gen_verilog_one_sb_module_name(size_t rr_sb_id);
char* gen_verilog_one_sb_instance_name(t_sb* cur_sb_info);
char* gen_verilog_one_routing_channel_module_name(t_rr_type chan_type,
int x, int y);
char* gen_verilog_one_routing_channel_instance_name(t_rr_type chan_type,
int x, int y);
char* gen_verilog_one_mux_module_name(t_spice_model* spice_model,
int mux_size);
char* gen_verilog_one_grid_instance_name(int grid_x, int grid_y);
char* gen_verilog_one_grid_module_name(int grid_x, int grid_y);
char* gen_verilog_one_block_instance_name(int grid_x, int grid_y, int grid_z);
char* gen_verilog_one_phy_block_instance_name(t_type_ptr cur_type_ptr,
int block_z);
char* gen_verilog_one_pb_graph_node_instance_name(t_pb_graph_node* cur_pb_graph_node);
char* gen_verilog_one_pb_type_pin_name(char* prefix,
t_port* cur_port, int pin_number);
char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy(t_pb_graph_pin* cur_pb_graph_pin);
char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_parent_node(t_pb_graph_pin* cur_pb_graph_pin);
char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node(t_pb_graph_pin* cur_pb_graph_pin);
char* gen_verilog_top_module_io_port_prefix(char* global_prefix,
char* io_port_prefix);
char* gen_verilog_one_pb_graph_node_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node);
#endif

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp
View File

@ -93,6 +93,7 @@ void print_verilog_wire_module(ModuleManager& module_manager,
* Top-level function to print wire modules
*******************************************************************/
void print_verilog_submodule_wires(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
@ -127,6 +128,6 @@ void print_verilog_submodule_wires(ModuleManager& module_manager,
/* Close the file stream */
fp.close();
/* Add fname to the linked list */
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
}

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h
View File

@ -15,6 +15,7 @@
#include "module_manager.h"
void print_verilog_submodule_wires(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);

26
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -1367,3 +1367,29 @@ void print_verilog_clock_stimuli(std::fstream& fp,
fp << std::endl;
}
/********************************************************************
* Output a header file that includes a number of Verilog netlists
* so that it can be easily included in a top-level netlist
********************************************************************/
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name) {
std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_handler(fp);
/* Generate the descriptions*/
print_verilog_file_header(fp, "Header file to include other Verilog netlists");
/* Output file names */
for (const std::string& netlist_name : netlists_to_be_included) {
fp << "`include \"" << netlist_name << "\"" << std::endl;
}
/* close file stream */
fp.close();
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h
View File

@ -168,4 +168,8 @@ void print_verilog_clock_stimuli(std::fstream& fp,
const float& pulse_width,
const std::string& wait_condition);
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name);
#endif