riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Architecture] Update external bitstream

This commit is contained in:
tangxifan 2020-09-25 21:30:59 -06:00
parent dcbd6a0614
commit ffd926d686
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
View File

@ -2,7 +2,7 @@
- Architecture independent bitstream - Architecture independent bitstream
- Author: Xifan TANG - Author: Xifan TANG
- Organization: University of Utah - Organization: University of Utah
- Date: Thu Sep 24 20:16:32 2020 - Date: Fri Sep 25 21:30:07 2020
--> -->
<bitstream_block name="fpga_top" hierarchy_level="0"> <bitstream_block name="fpga_top" hierarchy_level="0">
@ -1286,20 +1286,20 @@
</hierarchy> </hierarchy>
<bitstream> <bitstream>
<bit memory_port="mem_out[0]" value="1"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="1"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[3]" value="1"/> <bit memory_port="mem_out[3]" value="0"/>
<bit memory_port="mem_out[4]" value="1"/> <bit memory_port="mem_out[4]" value="1"/>
<bit memory_port="mem_out[5]" value="1"/> <bit memory_port="mem_out[5]" value="0"/>
<bit memory_port="mem_out[6]" value="1"/> <bit memory_port="mem_out[6]" value="1"/>
<bit memory_port="mem_out[7]" value="1"/> <bit memory_port="mem_out[7]" value="0"/>
<bit memory_port="mem_out[8]" value="1"/> <bit memory_port="mem_out[8]" value="0"/>
<bit memory_port="mem_out[9]" value="0"/> <bit memory_port="mem_out[9]" value="0"/>
<bit memory_port="mem_out[10]" value="1"/> <bit memory_port="mem_out[10]" value="0"/>
<bit memory_port="mem_out[11]" value="0"/> <bit memory_port="mem_out[11]" value="0"/>
<bit memory_port="mem_out[12]" value="1"/> <bit memory_port="mem_out[12]" value="0"/>
<bit memory_port="mem_out[13]" value="0"/> <bit memory_port="mem_out[13]" value="0"/>
<bit memory_port="mem_out[14]" value="1"/> <bit memory_port="mem_out[14]" value="0"/>
<bit memory_port="mem_out[15]" value="0"/> <bit memory_port="mem_out[15]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>