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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads

This commit is contained in:
tangxifan 2020-03-27 20:09:50 -06:00
parent e601a648cc
commit ff9cc50527
4 changed files with 144 additions and 139 deletions
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4
libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
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@ -462,7 +462,9 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_INOUT);
iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
/* Some I/Os may not have SRAM port, such as AIB interface
* iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
*/
num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_IOPAD, iopad_port_types_required);

5
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
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@ -88,9 +88,9 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
VTR_ASSERT(1 == operating_clock_ports.size());
/* In this function, we support only 1 type of I/Os */
VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
for (const BasicPort& module_io_port : module_io_ports) {
/* Keep tracking which I/Os have been used */
std::vector<bool> io_used(module_io_port.get_width(), false);
@ -166,6 +166,7 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
/* Add an empty line as a splitter */
fp << std::endl;
}
}
/********************************************************************
* Disable the timing for all the global port except the operating clock ports

5
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
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@ -132,10 +132,10 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
valid_file_stream(fp);
/* In this function, we support only 1 type of I/Os */
VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
/* Keep tracking which I/Os have been used */
for (const BasicPort& module_io_port : module_io_ports) {
std::vector<bool> io_used(module_io_port.get_width(), false);
/* See if this I/O should be wired to a benchmark input/output */
@ -213,6 +213,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
/* Add an empty line as a splitter */
fp << std::endl;
}
}
/********************************************************************
* Print Verilog codes to set up a timeout for the simulation

3
openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -209,7 +209,7 @@
<port type="output" prefix="d_out" size="32"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model>
<circuit_model type="hard_logic" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
<circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
@ -218,6 +218,7 @@
<port type="output" prefix="rx_data" size="80"/>
<port type="clock" prefix="tx_clk" size="1" default_val="0"/>
<port type="clock" prefix="rx_clk" size="1" default_val="0"/>
<port type="inout" prefix="pad" size="80"/>
</circuit_model>
</circuit_library>
<configuration_protocol>