updated ci_test

2021-07-01 16:23:55 +05:00 · 2021-07-01 16:23:55 +05:00 · ff785569f0
parent 2469f25ef4
commit ff785569f0
1 changed files with 1 additions and 1 deletions
--- a/ci_test.sh
+++ b/ci_test.sh
@ -15,7 +15,7 @@ for dir in RTL_Benchmark/*; do
 	  export design_path=${OPENFPGA_PATH}/$FILE
 	  export design_top=$top_file
 	  echo "design = $design_path"
-	  python3 openfpga_flow/scripts/run_ci_tests.py ci_tests
+	  python3 $OPENFPGA_PATH/openfpga_flow/scripts/run_ci_tests.py ci_tests
 	else  
 	  echo -e "${RED}Top file not found. Make sure design exists${ENDCOLOR}"
 	  exit 1