updated ci_test
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@ -15,7 +15,7 @@ for dir in RTL_Benchmark/*; do
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export design_path=${OPENFPGA_PATH}/$FILE
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export design_path=${OPENFPGA_PATH}/$FILE
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export design_top=$top_file
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export design_top=$top_file
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echo "design = $design_path"
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echo "design = $design_path"
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python3 openfpga_flow/scripts/run_ci_tests.py ci_tests
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python3 $OPENFPGA_PATH/openfpga_flow/scripts/run_ci_tests.py ci_tests
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else
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else
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echo -e "${RED}Top file not found. Make sure design exists${ENDCOLOR}"
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echo -e "${RED}Top file not found. Make sure design exists${ENDCOLOR}"
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exit 1
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exit 1
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