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OpenFPGA
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[core] syntax

This commit is contained in:
tangxifan 2023-02-27 22:39:12 -08:00
parent d4e19edc71
commit ff69664c14
2 changed files with 12 additions and 13 deletions
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8
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -244,7 +244,7 @@ std::vector<std::string> ClockNetwork::spine_flatten_taps(const ClockSpineId& sp
StringToken tokenizer(tap_name);
std::vector<std::string> pin_tokens = tokenizer.split(".");
if (pin_tokens.size() != 2) {
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n", pin_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n", tap_name.c_str());
exit(1);
}
PortParser tile_parser(pin_tokens[0]);
@ -252,11 +252,11 @@ std::vector<std::string> ClockNetwork::spine_flatten_taps(const ClockSpineId& sp
PortParser pin_parser(pin_tokens[1]);
BasicPort pin_info = pin_parser.port();
if (!tile_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", pin_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", tap_name.c_str());
exit(1);
}
if (!pin_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", pin_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", tap_name.c_str());
exit(1);
}
for (size_t& tile_idx : tile_info.pins()) {
@ -431,7 +431,7 @@ void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id,
void ClockNetwork::add_spine_tap(const ClockSpineId& spine_id, const std::string& pin_name) {
VTR_ASSERT(valid_spine_id(spine_id));
spine_taps_.push_back(pin_name);
spine_taps_[spine_id].push_back(pin_name);
}
bool ClockNetwork::link() {

17
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -363,7 +363,7 @@ void try_find_and_add_clock_track2ipin_node(std::vector<RRNodeId>& des_nodes,
const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type = grids[grid_coord.x()][grid_coord.y()].type;
for (std::string tap_pin_name : clk_ntwk.tap_pin_names(clk_tree, clk_pin)) {
for (std::string tap_pin_name : clk_ntwk.spine_flatten_taps(clk_tree, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */
int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name);
if (grid_pin_idx == grid_type->num_pins) {
@ -415,21 +415,20 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(const DeviceGrid& grids,
if (chan_type == CHANX) {
/* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */
vtr::Point<size_t> bot_grid_coord(chan_coord.x(), chan_coord.y() + 1);
try_find_and_add_clock_track2ipin_node(des_nodes, rr_graph_view, bot_grid_coord, BOTTOM, clk_ntwk, clk_tree, clk_pin);
}
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, bot_grid_coord, BOTTOM, clk_ntwk, clk_tree, clk_pin);
/* Get the clock IPINs at the TOP side of adjacent grids [x][y] */
vtr::Point<size_t> top_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, rr_graph_view, top_grid_coord, TOP, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, top_grid_coord, TOP, clk_ntwk, clk_tree, clk_pin);
} else {
VTR_ASSERT(chan_type == CHANY);
/* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */
vtr::Point<size_t> left_grid_coord(chan_coord.x() + 1, chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, rr_graph_view, left_grid_coord, LEFT, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, left_grid_coord, LEFT, clk_ntwk, clk_tree, clk_pin);
/* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */
vtr::Point<size_t> right_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, rr_graph_view, right_grid_coord, RIGHT, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, right_grid_coord, RIGHT, clk_ntwk, clk_tree, clk_pin);
}
return des_nodes;
@ -527,7 +526,7 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, clk_ntwk,
clk_rr_lookup, rr_graph_view, grids, clk_ntwk,
chanx_coord, CHANX);
}
}
@ -543,7 +542,7 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, clk_ntwk,
clk_rr_lookup, rr_graph_view, grids, clk_ntwk,
chany_coord, CHANY);
}
}