diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index ce8c57b92..e7582360d 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -84,8 +84,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --sho
 
 echo -e "Testing Secured FPGA fabrics";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
 
 echo -e "Testing Power-gating designs";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf
index 0b6f18163..bfaecd8a1 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf
@@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml
-openfpga_vpr_device_layout=2x2
+openfpga_vpr_device_layout=auto
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml