From fefcd88f142f156305793ebbf041407fb4bfe085 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 21:55:59 -0600 Subject: [PATCH] update openfpga architecture README for power-gating --- openfpga_flow/openfpga_arch/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index 0799af78e..2e5dede96 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -23,5 +23,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - stdcell: If circuit designs are built with standard cells only - tree\_mux: If routing multiplexers are built with a tree-like structure - : The technology node which the delay numbers are extracted from. +- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating. Other features are used in naming should be listed here.