From 6480b06a2dd851f64ec66b8237f54359b38f4b33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 11:01:53 -0600 Subject: [PATCH 001/330] [OpenFPGA tool] Remove out-of-data test blif, architecture and scripts --- openfpga/test_blif/and.act | 3 - openfpga/test_blif/and.blif | 8 - openfpga/test_blif/and.v | 14 - openfpga/test_blif/and_latch.act | 6 - openfpga/test_blif/and_latch.blif | 14 - openfpga/test_blif/and_latch.v | 23 - .../k6_N10_40nm_openfpga.xml | 228 ----- .../k6_frac_N10_40nm_openfpga.xml | 260 ------ .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 285 ------- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 302 ------- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 314 ------- ...c_N10_adder_column_chain_40nm_openfpga.xml | 285 ------- ...N10_adder_register_chain_40nm_openfpga.xml | 288 ------- ...dder_register_scan_chain_40nm_openfpga.xml | 294 ------- .../k6_frac_N10_spyio_40nm_openfpga.xml | 264 ------ .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 252 ------ .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 251 ------ openfpga/test_script/and_k6_frac.openfpga | 62 -- .../and_k6_frac_adder_chain.openfpga | 62 -- .../and_k6_frac_adder_chain_mem16K.openfpga | 62 -- .../test_script/and_k6_frac_tileable.openfpga | 59 -- .../and_k6_frac_tileable_adder_chain.openfpga | 64 -- ..._frac_tileable_adder_chain_mem16K.openfpga | 62 -- ...c_tileable_adder_chain_mem16K_aib.openfpga | 62 -- ...er_chain_mem16K_multi_io_capacity.openfpga | 62 -- ...ble_adder_chain_mem16K_reduced_io.openfpga | 62 -- ..._tileable_adder_chain_wide_mem16K.openfpga | 62 -- ..._frac_tileable_adder_column_chain.openfpga | 62 -- ...ileable_adder_register_scan_chain.openfpga | 63 -- .../and_k6_frac_tileable_spyio.openfpga | 59 -- ...and_k6_frac_tileable_stdcell_mux2.openfpga | 59 -- ...e_thru_channel_adder_chain_mem16K.openfpga | 62 -- .../and_k6_frac_tileable_tree_mux.openfpga | 59 -- .../test_script/and_latch_k6_frac.openfpga | 59 -- .../and_latch_k6_frac_tileable.openfpga | 59 -- ...atch_k6_frac_tileable_adder_chain.openfpga | 62 -- ..._frac_tileable_adder_chain_mem16K.openfpga | 62 -- openfpga/test_vpr_arch/k6_N10_40nm.xml | 299 ------- .../test_vpr_arch/k6_N10_tileable_40nm.xml | 299 ------- openfpga/test_vpr_arch/k6_frac_N10_40nm.xml | 441 ---------- .../k6_frac_N10_adder_chain_40nm.xml | 644 -------------- .../k6_frac_N10_adder_chain_mem16K_40nm.xml | 739 ---------------- .../k6_frac_N10_tileable_40nm.xml | 441 ---------- .../k6_frac_N10_tileable_adder_chain_40nm.xml | 644 -------------- ...c_N10_tileable_adder_chain_mem16K_40nm.xml | 739 ---------------- ...0_tileable_adder_chain_mem16K_aib_40nm.xml | 805 ------------------ ...er_chain_mem16K_multi_io_capacity_40nm.xml | 773 ----------------- ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 742 ---------------- ..._tileable_adder_chain_wide_mem16K_40nm.xml | 739 ---------------- ...N10_tileable_adder_register_chain_40nm.xml | 696 --------------- ...ileable_adder_register_scan_chain_40nm.xml | 734 ---------------- ...e_thru_channel_adder_chain_mem16K_40nm.xml | 734 ---------------- 52 files changed, 13785 deletions(-) delete mode 100644 openfpga/test_blif/and.act delete mode 100644 openfpga/test_blif/and.blif delete mode 100644 openfpga/test_blif/and.v delete mode 100644 openfpga/test_blif/and_latch.act delete mode 100644 openfpga/test_blif/and_latch.blif delete mode 100644 openfpga/test_blif/and_latch.v delete mode 100644 openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml delete mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml delete mode 100644 openfpga/test_script/and_k6_frac.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_spyio.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga delete mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga delete mode 100644 openfpga/test_vpr_arch/k6_N10_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml diff --git a/openfpga/test_blif/and.act b/openfpga/test_blif/and.act deleted file mode 100644 index 0f77bc6b3..000000000 --- a/openfpga/test_blif/and.act +++ /dev/null @@ -1,3 +0,0 @@ -a 0.5 0.5 -b 0.5 0.5 -c 0.25 0.25 diff --git a/openfpga/test_blif/and.blif b/openfpga/test_blif/and.blif deleted file mode 100644 index 67d978741..000000000 --- a/openfpga/test_blif/and.blif +++ /dev/null @@ -1,8 +0,0 @@ -.model top -.inputs a b -.outputs c - -.names a b c -11 1 - -.end diff --git a/openfpga/test_blif/and.v b/openfpga/test_blif/and.v deleted file mode 100644 index 876f1c6fe..000000000 --- a/openfpga/test_blif/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act deleted file mode 100644 index 61bbe1fe8..000000000 --- a/openfpga/test_blif/and_latch.act +++ /dev/null @@ -1,6 +0,0 @@ -a 0.492800 0.201000 -b 0.502000 0.197200 -clk 0.500000 2.000000 -d 0.240200 0.171200 -c 0.240200 0.044100 -n1 0.240200 0.044100 diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif deleted file mode 100644 index dbd863d9c..000000000 --- a/openfpga/test_blif/and_latch.blif +++ /dev/null @@ -1,14 +0,0 @@ -# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020 -.model top -.inputs a b clk -.outputs c d - -.latch n1 d re clk 0 - -.names a b c -11 1 - -.names c n1 -1 1 - -.end diff --git a/openfpga/test_blif/and_latch.v b/openfpga/test_blif/and_latch.v deleted file mode 100644 index 893cdf7a4..000000000 --- a/openfpga/test_blif/and_latch.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps - -module top( - clk, - a, - b, - c, - d); - -input wire clk; - -input wire a; -input wire b; -output wire c; -output reg d; - -assign c = a & b; - -always @(posedge clk) begin - d <= c; -end - -endmodule diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml deleted file mode 100644 index de0602e1e..000000000 --- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml +++ /dev/null @@ -1,228 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml deleted file mode 100644 index 51e250a8a..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ /dev/null @@ -1,260 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml deleted file mode 100644 index cb145e06d..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ /dev/null @@ -1,302 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml deleted file mode 100644 index 621847439..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ /dev/null @@ -1,294 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml deleted file mode 100644 index 159214507..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ /dev/null @@ -1,264 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml deleted file mode 100644 index 59f493a13..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ /dev/null @@ -1,252 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml deleted file mode 100644 index d04318510..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ /dev/null @@ -1,251 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga deleted file mode 100644 index 90f20b2b7..000000000 --- a/openfpga/test_script/and_k6_frac.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga deleted file mode 100644 index 3cdebb2b1..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga deleted file mode 100644 index 34ec11181..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga deleted file mode 100644 index 0731e6543..000000000 --- a/openfpga/test_script/and_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index 05ea64bce..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,64 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist - write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \ - --explicit_port_mapping --include_timing --include_signal_init \ - --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index ed0d8cc5a..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga deleted file mode 100644 index 492c70ea6..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga deleted file mode 100644 index 29830f1db..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga deleted file mode 100644 index 22a658a73..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga deleted file mode 100644 index 466c3bcd0..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga deleted file mode 100644 index fbcdda185..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga deleted file mode 100644 index 864fea78d..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga +++ /dev/null @@ -1,63 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc \ - --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga deleted file mode 100644 index 7b9fa407c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga deleted file mode 100644 index 04ff99d8c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga deleted file mode 100644 index 5b1177586..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga deleted file mode 100644 index 95cd2a3c3..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga deleted file mode 100644 index b41ac4450..000000000 --- a/openfpga/test_script/and_latch_k6_frac.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga deleted file mode 100644 index c89174d2d..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index ef49426d0..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index 87c69c880..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml deleted file mode 100644 index 83b4948a8..000000000 --- a/openfpga/test_vpr_arch/k6_N10_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml deleted file mode 100644 index ceacbb3f2..000000000 --- a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml deleted file mode 100644 index 8476a5155..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml deleted file mode 100644 index e0d7ce812..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml deleted file mode 100644 index 146a170e5..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml deleted file mode 100644 index 8f1dfd10e..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 8254a0583..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml deleted file mode 100644 index 35eedb327..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml +++ /dev/null @@ -1,805 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - 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- - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml deleted file mode 100644 index d23c34960..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +++ /dev/null @@ -1,773 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml deleted file mode 100644 index bb06c5f39..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +++ /dev/null @@ -1,742 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - 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io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml deleted file mode 100644 index f83919c7c..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin clb.scin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 7e4cf8e7a..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 951a47b19cb34fabbf215365bcb4ddff2434f1b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:05:39 -0600 Subject: [PATCH 002/330] [Architecture] Add k4 series architecture using pattern-based local routing --- ...N5_tileable_pattern_local_routing_40nm.xml | 355 ++++++++++++++++++ 1 file changed, 355 insertions(+) create mode 100644 openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml diff --git a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml new file mode 100644 index 000000000..29c20f59a --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml @@ -0,0 +1,355 @@ + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 1aab691e9d795b4e40408df5aed0d1c73e42b046 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:06:16 -0600 Subject: [PATCH 003/330] [Architecture] Add openfpga architecture using pattern based local routing --- ...tern_local_routing_40nm_frame_openfpga.xml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml new file mode 100644 index 000000000..2916fb658 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -0,0 +1,213 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 33506958061eaa6538f27b01e93775a5fe9b2977 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:06:47 -0600 Subject: [PATCH 004/330] [Regression test] Add test case for pattern based local routing architecture --- .../config/task.conf | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf new file mode 100644 index 000000000..2a94ee552 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 6ed05d380be1b807623298a713e713a167f4f709 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:08:01 -0600 Subject: [PATCH 005/330] [Regression Test] Deploy pattern based local routing test case to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 85cb514e4..515dc3b1d 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -51,5 +51,7 @@ echo -e "Testing K4N4 with multiple lengths of routing segments"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs echo -e "Testing K4N4 with 32-bit fracturable multiplier"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs +echo -e "Testing K4N5 with pattern based local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs end_section "OpenFPGA.TaskTun" From c92cf71891989fcdbce2c9e5c9907d29886048a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:46:41 -0600 Subject: [PATCH 006/330] [Regression Test] Add a new template script for fixed device support --- ...e_route_chan_width_example_script.openfpga | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga new file mode 100644 index 000000000..5bac56d00 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 149d5b20bd7d27a340570419721bd75ba042073f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:47:11 -0600 Subject: [PATCH 007/330] [Regression Test] Add test case for fixed device support --- .../fixed_device_support/config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf new file mode 100644 index 000000000..364962203 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 5c62bafa7ff780215d8b5ed535281c50320dcb7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 16:48:45 -0600 Subject: [PATCH 008/330] [Regression Test] Deploy the fix device test case to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 515dc3b1d..04ed06fe2 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -29,6 +29,9 @@ echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FP python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs +echo -e "Testing fixed device layout and routing channel width"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs + echo -e "Testing fabric Verilog generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs From b242ab79bd4125bd5cb2742c25b7a373a5814901 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:19:02 -0600 Subject: [PATCH 009/330] [OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset --- .../VerilogNetlists/config_latch_neg_rst.v | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_rst.v diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v new file mode 100644 index 000000000..917bf88ce --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -0,0 +1,39 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated at rising clock edge +// when wl is enabled +// Reset is active low +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch ( + input resetb, // Reset input + input clk, // Clock Input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or posedge resetb) begin + if (~resetb) begin + q_reg <= 1'b0; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule From 893859be370c45a149e4bfc9af9252cfefe3b07e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:21:00 -0600 Subject: [PATCH 010/330] [Architecture] Add openfpga architecture using active-low configurable latch --- .../k4_N4_40nm_frame_resetb_openfpga.xml | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml new file mode 100644 index 000000000..27df66764 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From a94c2655c2863e194785fe75d5e3ebaeb7616e75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:21:30 -0600 Subject: [PATCH 011/330] [Architecture] Patch Verilog HDL for configurable latch --- openfpga_flow/VerilogNetlists/config_latch.v | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index 6cbe5657e..ec52510d6 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -4,6 +4,7 @@ // Function : A Configurable Latch where data storage // can be updated at rising clock edge // when wl is enabled +// Reset is active high // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( From f23c25e1234b99ea88bf95a2b520a78bf207d77d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:25:17 -0600 Subject: [PATCH 012/330] [Regression Test] Add test case for configurable latch with active-low reset --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf new file mode 100644 index 000000000..755b9ec94 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From a3c982a83f896061b008865b689c5c5080897e95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:27:16 -0600 Subject: [PATCH 013/330] [Architecture] Patch the openfpga architecture using active-low configurable latch --- .../openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml index 27df66764..efefbf581 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -146,7 +146,7 @@ - + From f0d31f50f4b5df23e6e7f3f366e5f0abd1406251 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:28:36 -0600 Subject: [PATCH 014/330] [Regression Test] Deploy active-low configurable latch test case to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 04ed06fe2..f61ddb698 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,6 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs From 1a2c66f07de63cfcc1a827200d5a51ae1827fdf3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:34:49 -0600 Subject: [PATCH 015/330] [Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell --- .../k4_N4_40nm_frame_sram_openfpga.xml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml new file mode 100644 index 000000000..a21f2a520 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From ad385c6d69de01d16ee5de736f8cc3a87cf43d7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:39:36 -0600 Subject: [PATCH 016/330] [Regression Test] Add test case for using SRAM cell in frame-based configuration --- .../configuration_frame_sram/config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf new file mode 100644 index 000000000..1e7322490 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 092ada39f4a77b85f2f4eff69ddfa71ec34a88ed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:49:30 -0600 Subject: [PATCH 017/330] [Architecture] Add Verilog HDL for DFF with write enable --- openfpga_flow/VerilogNetlists/ff_en.v | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/ff_en.v diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v new file mode 100644 index 000000000..fa0ed47d4 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -0,0 +1,33 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flop with Write Enable +// File Name : ff_en.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module DFF_EN ( +/* Global ports go first */ +input SET, // set input +input RST, // Reset input +input WE, // Write Enable +input CK, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RESET) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (WE) begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; + +endmodule //End Of Module From 645db17168268a300e78d57a26191c54a16c78a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:52:59 -0600 Subject: [PATCH 018/330] [Architecture] Patch DFF Verilog HDL --- openfpga_flow/VerilogNetlists/ff_en.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v index fa0ed47d4..c7a063ce7 100644 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -13,6 +13,7 @@ input CK, // Clock Input /* Local ports follow */ input D, // Data Input output Q // Q output +output QB // QB output ); //------------Internal Variables-------- reg q_reg; @@ -27,7 +28,13 @@ end else if (WE) begin q_reg <= D; end +`ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q assign Q = q_reg; +assign QB = ~q_reg; +`else +assign Q = 1'bZ; +assign QB = !Q; +`endif endmodule //End Of Module From 906191e9310faeb9d3c87613c1f306f9c137f0d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 17:58:13 -0600 Subject: [PATCH 019/330] [Architecture] Use strict latch Verilog HDL in frame-based procotol --- openfpga_flow/VerilogNetlists/config_latch.v | 6 ++---- .../VerilogNetlists/config_latch_neg_rst.v | 6 ++---- ...xml => k4_N4_40nm_frame_ccff_openfpga.xml} | 19 +++++++++++-------- .../k4_N4_40nm_frame_openfpga.xml | 1 - .../k4_N4_40nm_frame_resetb_openfpga.xml | 1 - .../k4_N4_40nm_powergate_frame_openfpga.xml | 1 - ...4_no_local_routing_40nm_frame_openfpga.xml | 1 - ...tern_local_routing_40nm_frame_openfpga.xml | 1 - ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 1 - ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 1 - ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 1 - .../config/task.conf | 2 +- 12 files changed, 16 insertions(+), 25 deletions(-) rename openfpga_flow/openfpga_arch/{k4_N4_40nm_frame_sram_openfpga.xml => k4_N4_40nm_frame_ccff_openfpga.xml} (90%) rename openfpga_flow/tasks/basic_tests/full_testbench/{configuration_frame_sram => configuration_frame_ccff}/config/task.conf (97%) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index ec52510d6..e0732ac47 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -2,14 +2,12 @@ // Design Name : config_latch // File Name : config_latch.v // Function : A Configurable Latch where data storage -// can be updated at rising clock edge -// when wl is enabled +// can be updated when wl is enabled // Reset is active high // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( input reset, // Reset input - input clk, // Clock Input input wl, // Data Enable input bl, // Data Input output Q, // Q output @@ -19,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset) begin +always @ ( posedge reset) begin if (reset) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v index 917bf88ce..836012259 100644 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -2,14 +2,12 @@ // Design Name : config_latch // File Name : config_latch.v // Function : A Configurable Latch where data storage -// can be updated at rising clock edge -// when wl is enabled +// can be updated when wl is enabled // Reset is active low // Coder : Xifan TANG //----------------------------------------------------- module config_latch ( input resetb, // Reset input - input clk, // Clock Input input wl, // Data Enable input bl, // Data Input output Q, // Q output @@ -19,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge resetb) begin +always @ ( posedge resetb) begin if (~resetb) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml similarity index 90% rename from openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index a21f2a520..48fc4157c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -145,28 +145,31 @@ - + + - - - - - + + + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index b89a23644..b370c1f3d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml index efefbf581..f1894c9a5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index bf96e1aa0..402331b6f 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -161,7 +161,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 9ba39b3ce..c579e4f49 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 2916fb658..7ca1ba958 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -155,7 +155,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 508ceab90..45d660d95 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 8bba60744..6a3aba09e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index eb5e3c659..0cd86c659 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -173,7 +173,6 @@ - diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf similarity index 97% rename from openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf index 1e7322490..399be683b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_sram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_sram_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From ebb866d04a55c200f3b69a90ed709ca5fbc0c008 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:04:14 -0600 Subject: [PATCH 020/330] [Architecture] Patch frame based using ccff --- openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 48fc4157c..286b20f38 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + From 341a7578310b7e9eb71f50e91ea1f6205e1bd2f3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:05:55 -0600 Subject: [PATCH 021/330] [Regression Test] Deploy configuration frame using ccff test case to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index f61ddb698..efca9e376 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,6 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From 9adeb550dc60d25aa9e9caa9b4ab9d996200c067 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:28:00 -0600 Subject: [PATCH 022/330] [OpenFPGA Tool] Bug fix in fabric builder --- openfpga/src/fabric/build_memory_modules.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp index b9b83508a..32d1c93b2 100644 --- a/openfpga/src/fabric/build_memory_modules.cpp +++ b/openfpga/src/fabric/build_memory_modules.cpp @@ -636,13 +636,13 @@ void build_frame_memory_module(ModuleManager& module_manager, module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance); /* Wire data_in port to SRAM BL port */ - ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0])); + ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_bl_ports[0])); add_module_bus_nets(module_manager, mem_module, mem_module, 0, mem_data_port, sram_mem_module, sram_instance, sram_bl_port); /* Wire decoder data_out port to sram WL ports */ - ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0])); + ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_wl_ports[0])); ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); ModuleNetId wl_net = module_manager.create_module_net(mem_module); /* Source node of the input net is the input of memory module */ From 1864b080a23ad10a26ab2e1eb44933904757300d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:28:45 -0600 Subject: [PATCH 023/330] [Architecture] Bug fix in configurable latch Verilog HDL --- openfpga_flow/VerilogNetlists/config_latch.v | 2 +- openfpga_flow/VerilogNetlists/ff_en.v | 4 ++-- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index e0732ac47..e08ea2153 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -17,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge reset) begin +always @ (reset or bl or wl) begin if (reset) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v index c7a063ce7..11b657a9f 100644 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ b/openfpga_flow/VerilogNetlists/ff_en.v @@ -12,7 +12,7 @@ input WE, // Write Enable input CK, // Clock Input /* Local ports follow */ input D, // Data Input -output Q // Q output +output Q, // Q output output QB // QB output ); //------------Internal Variables-------- @@ -20,7 +20,7 @@ reg q_reg; //-------------Code Starts Here--------- always @ ( posedge CK or posedge RST or posedge SET) -if (RESET) begin +if (RST) begin q_reg <= 1'b0; end else if (SET) begin q_reg <= 1'b1; diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 286b20f38..7ccada510 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + From 129caea38cb93afe977358a7a065cdb1ff87ec6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:30:48 -0600 Subject: [PATCH 024/330] [Architecture] Patch configurable latch Verilog HDL with resetb --- openfpga_flow/VerilogNetlists/config_latch_neg_rst.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v index 836012259..cb24769d5 100644 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -17,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge resetb) begin +always @ (resetb or wl or bl) begin if (~resetb) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin From ad881ea4dc1a43404187ba4c6159ae35d8ea324b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:59:25 -0600 Subject: [PATCH 025/330] [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank --- .../src/fpga_verilog/verilog_top_testbench.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 27f714957..8a5ec3721 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -136,15 +136,15 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); } @@ -173,15 +173,16 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } /******************************************************************** From 437ef544313ec88439eff88d6a35911cd63f128f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 19:20:41 -0600 Subject: [PATCH 026/330] [Regression Test] Bug fix for CI --- .travis/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index efca9e376..e0ee4685b 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -19,7 +19,7 @@ echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From 8e4e66038a532867722bc71c034eba87d0a82112 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 19:32:48 -0600 Subject: [PATCH 027/330] [Architecture] Bug fix for standalone memory --- openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 035732d35..0781e6caa 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -155,7 +155,6 @@ - From 064678fe32c455222acd19763036b2b97f778cd9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:27:52 -0600 Subject: [PATCH 028/330] [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol --- .../libarchopenfpga/src/circuit_library.cpp | 15 ++++++ .../libarchopenfpga/src/circuit_library.h | 23 +++++---- .../src/read_xml_circuit_library.cpp | 3 ++ .../src/write_xml_circuit_library.cpp | 4 ++ openfpga/src/base/openfpga_verilog.cpp | 2 +- openfpga/src/fpga_verilog/verilog_api.cpp | 6 +-- openfpga/src/fpga_verilog/verilog_api.h | 3 +- .../fpga_verilog/verilog_top_testbench.cpp | 51 ++++++++++++++----- .../src/fpga_verilog/verilog_top_testbench.h | 3 +- 9 files changed, 81 insertions(+), 29 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index bbf9c50c4..1bc6e840e 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,6 +942,12 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } +bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_edge_triggered_[circuit_port_id]; +} + /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ @@ -1493,6 +1499,15 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } +/* Set the is_edge_triggered for a port of a circuit model */ +void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered) { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; + return; +} + /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index bd082f738..f4b742a27 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,15 +91,16 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 15. port_inv_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop + * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 16. port_inv_model_names_: the name of inverter circuit model linked to the port + * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -284,6 +285,7 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; + bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -364,6 +366,8 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); + void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -550,6 +554,7 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; + vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 36e837814..4136b0463 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,6 +564,9 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Identify if the port is to triggered by edges, by default it is NOT */ + circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index b141b0fe2..9165725e2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,6 +207,10 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } + if (true == circuit_lib.port_is_edge_triggered(port)) { + write_xml_attribute(fp, "is_edge_triggered", "true"); + } + /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str()); diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 58ea20f2e..0c6367fc5 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -97,7 +97,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.simulation_setting(), - openfpga_ctx.arch().config_protocol.type(), + openfpga_ctx.arch().config_protocol, options); /* TODO: should identify the error code from internal function execution */ diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index 940d78953..fe5b76196 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -156,7 +156,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, const VprNetlistAnnotation &netlist_annotation, const CircuitLibrary &circuit_lib, const SimulationSetting &simulation_setting, - const e_config_protocol_type &config_protocol_type, + const ConfigProtocol &config_protocol, const VerilogTestbenchOption &options) { vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n"); @@ -205,7 +205,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, - config_protocol_type, + config_protocol, circuit_lib, global_ports, atom_ctx, place_ctx, io_location_map, netlist_annotation, @@ -225,7 +225,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, src_dir_path, atom_ctx, place_ctx, io_location_map, module_manager, - config_protocol_type, + config_protocol.type(), bitstream_manager.num_bits(), simulation_setting.num_clock_cycles(), simulation_setting.programming_clock_frequency(), diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 94fbf3a29..1af656d7d 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -10,6 +10,7 @@ #include "mux_library.h" #include "decoder_library.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "vpr_device_annotation.h" #include "device_rr_gsb.h" @@ -49,7 +50,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const CircuitLibrary& circuit_lib, const SimulationSetting& simulation_parameters, - const e_config_protocol_type& config_protocol_type, + const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 8a5ec3721..763f7800e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -153,6 +153,8 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { /* Validate the file stream */ @@ -174,15 +176,32 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; /* Wire the INVERTED configuration done signal to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); + /* Find the circuit model of configurable memory + * Spot its BL port and generate stimuli based on BL port's attribute: + * - If the BL port is triggered by edge, use the inverted programming clock signal + * - If the BL port is a regular port, use the inverted configuration done signal + */ + const CircuitModelId& mem_model = config_protocol.memory_model(); + VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model)); + std::vector mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL); + VTR_ASSERT(1 == mem_model_bl_ports.size()); + if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + } else { + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } } /******************************************************************** @@ -190,10 +209,11 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { - switch(sram_orgz_type) { + switch(config_protocol.type()) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module); break; @@ -204,7 +224,8 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module); + print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib, + module_manager, top_module); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -435,7 +456,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const std::string& circuit_name){ /* Validate the file stream */ valid_file_stream(fp); @@ -509,7 +531,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type, + print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib, module_manager, top_module); /* Create a clock port if the benchmark have one but not in the default name! @@ -1459,7 +1481,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, @@ -1498,13 +1520,14 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, - sram_orgz_type, circuit_name); + config_protocol, circuit_lib, + circuit_name); /* Find the clock period */ float prog_clock_period = (1./simulation_parameters.programming_clock_frequency()); float op_clock_period = (1./simulation_parameters.operating_clock_frequency()); /* Estimate the number of configuration clock cycles */ - size_t num_config_clock_cycles = calculate_num_config_clock_cycles(sram_orgz_type, + size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(), fast_configuration, bitstream_manager, fabric_bitstream); @@ -1543,11 +1566,11 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Print tasks used for loading bitstreams */ print_verilog_top_testbench_load_bitstream_task(fp, - sram_orgz_type, + config_protocol.type(), module_manager, top_module); /* load bitstream to FPGA fabric in a configuration phase */ - print_verilog_top_testbench_bitstream(fp, sram_orgz_type, + print_verilog_top_testbench_bitstream(fp, config_protocol.type(), fast_configuration, module_manager, top_module, bitstream_manager, fabric_bitstream); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index cbafc6dc4..64d0e0b26 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -10,6 +10,7 @@ #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "io_location_map.h" #include "vpr_netlist_annotation.h" @@ -25,7 +26,7 @@ namespace openfpga { void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, From 3d234d840b051322479e4b132238e121b65eb5d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:31:11 -0600 Subject: [PATCH 029/330] [Documentation] Update documentation for the edge triggered attribute --- docs/source/manual/arch_lang/circuit_library.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 59e5f055f..9e8466c09 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" + is_edge_triggered="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -190,6 +191,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. + .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details. From 8b8ce22fd1fda5d5bf16be3003561bb4fd774d8b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:37:28 -0600 Subject: [PATCH 030/330] [OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library --- libopenfpga/libarchopenfpga/src/circuit_library.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 1bc6e840e..d8069f903 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -1380,6 +1380,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); + port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); From fc60b181914a7169b8af801d773de6dfa9160665 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:41:49 -0600 Subject: [PATCH 031/330] [Architecture] Now a regular flip-flop can be used in frame-based configuration --- .../k4_N4_40nm_frame_ccff_openfpga.xml | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 7ccada510..f6313bc22 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,30 +146,28 @@ - + - - + - + - - + - + - + From 2869eae8a94958322b84471408278152693665f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:43:15 -0600 Subject: [PATCH 032/330] [Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol --- .../k4_N4_40nm_frame_scff_openfpga.xml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml new file mode 100644 index 000000000..7ccada510 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 05c2e652a44e0f236c21e86d4a3b5a04c78ce365 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:44:06 -0600 Subject: [PATCH 033/330] [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol --- .../configuration_frame_scff/config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf new file mode 100644 index 000000000..2be6528e4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 709a20a3499f07c34a86bc1c918ce7839dfeff52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:45:19 -0600 Subject: [PATCH 034/330] [Regression Test] Deploy new test to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index e0ee4685b..609c60749 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -20,6 +20,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; From a3abf81afec540cf908002546eb462ec5b40407a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:25:06 -0600 Subject: [PATCH 035/330] [OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration --- .../fpga_verilog/verilog_top_testbench.cpp | 135 ++++++++++++++++-- 1 file changed, 127 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 763f7800e..d6f7d1075 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1135,6 +1135,89 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } +/******************************************************************** + * Decide if we should use reset or set signal to acheive fast configuration + * - If only one type signal is specified, we use that type + * For example, only reset signal is defined, we will use reset + * - If both are defined, pick the one that will bring bigger reduction + * i.e., larger number of configuration bits can be skipped + *******************************************************************/ +static +bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, + const bool& fast_configuration, + const std::vector& global_prog_reset_ports, + const std::vector& global_prog_set_ports, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + + /* Early exit conditions */ + if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) { + return false; + } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + return true; + } else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + /* If both types of ports are not defined, the fast configuration should be turned off */ + VTR_ASSERT(false == fast_configuration); + return false; + } + + VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); + bool bit_value_to_skip = false; + + size_t num_ones_to_skip = 0; + size_t num_zeros_to_skip = 0; + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: { + /* We can only skip the ones/zeros at the beginning of the bitstream */ + /* Count how many logic '1' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + /* Count how many logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_zeros_to_skip++; + } + break; + } + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + /* Count how many logic '1' and logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + num_zeros_to_skip++; + } else { + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + } + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid SRAM organization type!\n"); + exit(1); + } + + /* By default, we prefer to skip zeros (when the numbers are the same */ + if (num_ones_to_skip > num_zeros_to_skip) { + bit_value_to_skip = true; + } + + return bit_value_to_skip; +} + /******************************************************************** * Print stimulus for a FPGA fabric with a configuration chain protocol * where configuration bits are programming in serial (one by one) @@ -1150,6 +1233,7 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, static void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ @@ -1174,13 +1258,14 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << std::endl; + /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) */ bool start_config = false; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { if ( (false == start_config) - && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { + && (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { start_config = true; } @@ -1221,6 +1306,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, static void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1272,7 +1358,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1326,6 +1412,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, static void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1368,7 +1455,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1424,30 +1511,61 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_bitstream(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const e_config_protocol_type& config_protocol_type, const bool& fast_configuration, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, const ModuleManager& module_manager, const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { + /* Try to find global reset/set ports for programming */ + std::vector global_prog_reset_ports; + std::vector global_prog_set_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_reset(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { + global_prog_reset_ports.push_back(global_port); + } + if (true == circuit_lib.port_is_set(global_port)) { + global_prog_set_ports.push_back(global_port); + } + } + + bool apply_fast_configuration = fast_configuration; + if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) + && (true == fast_configuration)) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off"); + } + bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, + apply_fast_configuration, + global_prog_reset_ports, + global_prog_set_ports, + bitstream_manager, fabric_bitstream); + /* Branch on the type of configuration protocol */ - switch (sram_orgz_type) { + switch (config_protocol_type) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_vanilla_bitstream(fp, module_manager, top_module, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, + print_verilog_top_testbench_configuration_chain_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, + print_verilog_top_testbench_memory_bank_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, + print_verilog_top_testbench_frame_decoder_bitstream(fp, apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; @@ -1572,6 +1690,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* load bitstream to FPGA fabric in a configuration phase */ print_verilog_top_testbench_bitstream(fp, config_protocol.type(), fast_configuration, + circuit_lib, global_ports, module_manager, top_module, bitstream_manager, fabric_bitstream); From f57fd273afb14d766ad77a8de495c60e648b89b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:28:06 -0600 Subject: [PATCH 036/330] [Documentation] Update documentation for smart fast configuration --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c2044cf57..24dc3a603 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -33,6 +33,8 @@ write_verilog_testbench - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. + - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification From c2c37d7555944a0daca30b7083b104ba990e8e72 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:34:23 -0600 Subject: [PATCH 037/330] [OpenFPGA Tool] Add more print-out for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index d6f7d1075..28200696e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1164,6 +1164,8 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); bool bit_value_to_skip = false; + VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); + size_t num_ones_to_skip = 0; size_t num_zeros_to_skip = 0; @@ -1210,9 +1212,20 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& exit(1); } + VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), + num_zeros_to_skip, fabric_bitstream.num_bits()); + + VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), + num_ones_to_skip, fabric_bitstream.num_bits()); + /* By default, we prefer to skip zeros (when the numbers are the same */ if (num_ones_to_skip > num_zeros_to_skip) { + VTR_LOG("Will use set signal in fast configuration\n"); bit_value_to_skip = true; + } else { + VTR_LOG("Will use reset signal in fast configuration\n"); } return bit_value_to_skip; From 154c9045f6aa53f2567d7165ba87b32d7d3137fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:38:42 -0600 Subject: [PATCH 038/330] [OpoenFPGA Tool] Bug fix for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 28200696e..481d01ae4 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1536,10 +1536,13 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, std::vector global_prog_reset_ports; std::vector global_prog_set_ports; for (const CircuitPortId& global_port : global_ports) { + if (false == circuit_lib.port_is_reset(global_port)) { + continue; + } VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) || (false == circuit_lib.port_is_reset(global_port))); - if (true == circuit_lib.port_is_reset(global_port)) { + if (true == circuit_lib.port_is_prog(global_port)) { global_prog_reset_ports.push_back(global_port); } if (true == circuit_lib.port_is_set(global_port)) { From 8fa4fa1125a37fcd13af15265369056b0c8b6c11 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:39:31 -0600 Subject: [PATCH 039/330] [Architecture] Add openfpga architecture using set signals for configurable latch --- .../k4_N4_40nm_frame_use_set_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml new file mode 100644 index 000000000..a3ea99857 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7591060fbd24bde23552be77fb269b298efa3a24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:45:06 -0600 Subject: [PATCH 040/330] [Architecture] Add configurable latch Verilog designs and assoicated architectures --- .../VerilogNetlists/config_latch_set.v | 37 +++++++++++++++++ .../VerilogNetlists/config_latch_set_reset.v | 41 +++++++++++++++++++ .../k4_N4_40nm_frame_use_set_openfpga.xml | 6 +-- 3 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_set.v create mode 100644 openfpga_flow/VerilogNetlists/config_latch_set_reset.v diff --git a/openfpga_flow/VerilogNetlists/config_latch_set.v b/openfpga_flow/VerilogNetlists/config_latch_set.v new file mode 100644 index 000000000..945df2377 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_set.v @@ -0,0 +1,37 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Set is active high +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_set ( + input set, // Reset input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (set or bl or wl) begin + if (set) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v new file mode 100644 index 000000000..ad9f75322 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v @@ -0,0 +1,41 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Reset is active high +// Set is active high +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_set_reset ( + input reset, // Reset input + input set, // Set input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (reset or set or bl or wl) begin + if (reset) begin + q_reg <= 1'b0; + end else if (set) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index a3ea99857..2785712a8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,7 +146,7 @@ - + @@ -161,13 +161,13 @@ - + - + From 9331ef941d81dd3ea8f96a302571700be35acae2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:46:04 -0600 Subject: [PATCH 041/330] [Architecture] Add architecture that use both set and reset signals --- ...40nm_frame_use_both_set_reset_openfpga.xml | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..1f4108593 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 349aa79069ee79feadad2915c74f0c60f0c350f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:49:38 -0600 Subject: [PATCH 042/330] [Regression test] Add test case for smart fast configuration --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf new file mode 100644 index 000000000..1cdffa78f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 73e59d67afeb4551256c31d62fbe9ece9ce240b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:50:23 -0600 Subject: [PATCH 043/330] [Architecture] Add test case for fast configuration using set signals --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..4b5763f69 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From fcf1ff418fa949e7512f0f4b16478df944f80d1c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:53:38 -0600 Subject: [PATCH 044/330] [Architecture] Add Verilog for SRAM using set/reset --- openfpga_flow/VerilogNetlists/sram.v | 80 +++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index c27dbeebe..0cd5862c1 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -17,7 +17,7 @@ output outb // Data output reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(bl or wl) begin if (1'b1 == reset) begin data <= 1'b0; @@ -42,6 +42,84 @@ output outb // Data output endmodule +module sram_blwl_set( +input set, // Word line control signal +input wl, // Word line control signal +input bl, // Bit line control signal +output out, // Data output +output outb // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(bl or wl) + begin + if (1'b1 == set) begin + data <= 1'b1; + end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign out = data; + assign outb = ~data; +`else + assign out = 1'bZ; + assign outb = !out; +`endif + +endmodule + +module sram_blwl_set_reset( +input reset, // Word line control signal +input set, // Word line control signal +input wl, // Word line control signal +input bl, // Bit line control signal +output out, // Data output +output outb // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(bl or wl) + begin + if (1'b1 == reset) begin + data <= 1'b0; + end else if (1'b1 == set) begin + data <= 1'b1; + end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign out = data; + assign outb = ~data; +`else + assign out = 1'bZ; + assign outb = !out; +`endif + +endmodule + + //------ Module: sram6T_blwl -----// //------ Verilog file: sram.v -----// From 46b12611a9f4ed950951bc1baf49a8cbf29439cd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:04:07 -0600 Subject: [PATCH 045/330] [OpenFPGA Tool] Bug fix for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 481d01ae4..e76c198e9 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1536,13 +1536,14 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, std::vector global_prog_reset_ports; std::vector global_prog_set_ports; for (const CircuitPortId& global_port : global_ports) { - if (false == circuit_lib.port_is_reset(global_port)) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { continue; } - VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) - || (false == circuit_lib.port_is_reset(global_port))); - if (true == circuit_lib.port_is_prog(global_port)) { + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { global_prog_reset_ports.push_back(global_port); } if (true == circuit_lib.port_is_set(global_port)) { @@ -1553,7 +1554,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, bool apply_fast_configuration = fast_configuration; if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) && (true == fast_configuration)) { - VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off"); + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); } bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, apply_fast_configuration, From 77a1f995648792903da3087a004b29f39b31b8ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:04:24 -0600 Subject: [PATCH 046/330] [Architecture] Bug fix for architecture using set only --- .../openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index 2785712a8..96073d685 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,7 +146,7 @@ - + From 707300a6e4507bce0f0d5bf84de64c0269748101 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:07:40 -0600 Subject: [PATCH 047/330] [Architecture] Bug fix for using both reset and set architecture --- .../k4_N4_40nm_frame_use_both_set_reset_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 1f4108593..2b695027a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -146,7 +146,7 @@ - + From 07198f63960d2897af2e3bfdd1a2d94b4bb07091 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:08:30 -0600 Subject: [PATCH 048/330] [Regression Test] Deploy smart configuration tests to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 609c60749..04b36b885 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -17,7 +17,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/c echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs From c7fc0178b0b5f513b3f9a8a26d895c9166ade80f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:57:06 -0600 Subject: [PATCH 049/330] [Architecture] Rename to be consist with other architectures --- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml new file mode 100644 index 000000000..f1894c9a5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From d0cef6824265b274b8b570a4fd4025c8a96cdf3b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:58:59 -0600 Subject: [PATCH 050/330] [Regression test] Add test case for using resetb --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf new file mode 100644 index 000000000..24751ed47 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 8e780635df5781eb5a92cafcfa9b5ca59d53adb8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 22:59:46 -0600 Subject: [PATCH 051/330] [Regression Test] Rename test case in CI --- .travis/basic_reg_test.sh | 2 +- .../k4_N4_40nm_frame_resetb_openfpga.xml | 199 ------------------ .../config/task.conf | 34 --- 3 files changed, 1 insertion(+), 234 deletions(-) delete mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml delete mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 04b36b885..d22568aee 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -23,7 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_c python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml deleted file mode 100644 index f1894c9a5..000000000 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml +++ /dev/null @@ -1,199 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf deleted file mode 100644 index 755b9ec94..000000000 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_resetb/config/task.conf +++ /dev/null @@ -1,34 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=yosys_vpr - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_resetb_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench0_chan_width = 300 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= From 5d60b4ef8c27b7088008d7e596354a25ca1e6a95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:02:49 -0600 Subject: [PATCH 052/330] [Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set --- .../VerilogNetlists/config_latch_neg_set.v | 37 ++++ .../k4_N4_40nm_frame_use_setb_openfpga.xml | 199 ++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_set.v create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v new file mode 100644 index 000000000..2c23a73d1 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v @@ -0,0 +1,37 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Reset is active low +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_neg_set ( + input setb, // Reset input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (setb or wl or bl) begin + if (~setb) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml new file mode 100644 index 000000000..670339321 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 5b0d451f0fec4418390d0ee3fb4245c2fb2c6686 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:04:10 -0600 Subject: [PATCH 053/330] [Regression Test] Add test case for configurable latch with active-low set --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf new file mode 100644 index 000000000..793854774 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 10b6e1dc0dd5731b05b2e1d3d1c7c0077ccb715f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:06:46 -0600 Subject: [PATCH 054/330] [Architecture] bug fix for active-low --- .../openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 670339321..0a08f0b83 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -161,13 +161,13 @@ - + - + From 70a8c6dc29b350fe6a9c68c0a68f6f3f193595dc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:07:19 -0600 Subject: [PATCH 055/330] [Regression Test] Add test case using active-low set to CI --- .travis/basic_reg_test.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index d22568aee..5ffbcf6b2 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -20,10 +20,11 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs From 6bb30ab33c53b174f02f095352f922deb5b2d445 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:02:51 -0600 Subject: [PATCH 056/330] [Architecture] Enrich SRAM Verilog HDL for flexible set/reset support --- openfpga_flow/VerilogNetlists/sram.v | 261 +++++++++++++++++++++------ 1 file changed, 201 insertions(+), 60 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 0cd5862c1..847e1a90a 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -42,27 +42,32 @@ output outb // Data output endmodule -module sram_blwl_set( -input set, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMS( + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(D or WE) begin - if (1'b1 == set) begin + if (1'b1 == SET) begin data <= 1'b1; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -70,39 +75,83 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule -module sram_blwl_set_reset( -input reset, // Word line control signal -input set, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSN( + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(D or WE) begin - if (1'b1 == reset) begin + if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - a write-enable +//----------------------------------------------------- +module SRAMR( + input RST, // active-high reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin data <= 1'b0; - end else if (1'b1 == set) begin - data <= 1'b1; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -110,58 +159,150 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule - - -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module sram6T_blwl( -//input read, -//input nequalize, -input din, // Data input -output dout, // Data output -output doutb, // Data output -input bl, // Bit line control signal -input wl, // Word line control signal -input blb // Inverted Bit line control signal +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - a write-enable +//----------------------------------------------------- +module SRAMRN( + input RSTN, // active-low reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); + //----- local variable need to be registered - reg a; + reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(D or WE) begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 - if ((1'b1 == bl)&&(1'b1 == wl)) begin - a <= 1'b1; - end + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 - if ((1'b0 == bl)&&(1'b1 == wl)) begin - a <= 1'b0; + data <= 1'b0; end end - // dout is short-wired to din - assign dout = a; - //---- doutb is always opposite to dout - assign doutb = ~dout; -`ifdef ENABLE_SIGNAL_INITIALIZATION - initial begin - $deposit(a, $random); - end +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; `endif + endmodule +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMSR( + input RST, // active-high reset signal + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin + data <= 1'b0; + end else if (1'b1 == SET) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSNRN( + input RSTN, // active-low reset signal + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !out; +`endif + +endmodule + + module sram6T_rram( input read, input nequalize, From 56c9aab190d1772fcabe28af22dfcd5cc931a093 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:15:08 -0600 Subject: [PATCH 057/330] [Architecture] Add architecture to use different SRAM cells for memory bank --- ..._40nm_bank_use_both_set_reset_openfpga.xml | 200 ++++++++++++++++++ .../k4_N4_40nm_bank_use_reset_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_set_openfpga.xml | 199 +++++++++++++++++ .../k4_N4_40nm_bank_use_setb_openfpga.xml | 199 +++++++++++++++++ 5 files changed, 996 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..95c93a6db --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml new file mode 100644 index 000000000..33581d64a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml new file mode 100644 index 000000000..184c5b14c --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml new file mode 100644 index 000000000..904ee811a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml new file mode 100644 index 000000000..68a29312a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 186f00edfcddc7f9c1c1a5097af5059c936c8350 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:25:03 -0600 Subject: [PATCH 058/330] [Regression Test] Add test cases for memory bank using different SRAM cells --- .../memory_bank_use_reset/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_resetb/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_set/config/task.conf | 34 +++++++++++++++++++ .../memory_bank_use_setb/config/task.conf | 34 +++++++++++++++++++ .../smart_fast_memory_bank/config/task.conf | 34 +++++++++++++++++++ 5 files changed, 170 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf new file mode 100644 index 000000000..cb9ddbee7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf new file mode 100644 index 000000000..87ef8b32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..cf4341928 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf new file mode 100644 index 000000000..55af9d7cc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf new file mode 100644 index 000000000..26e5b6239 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From e454467799392dea4bd62e5e59a73d52c11a8fb1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:26:10 -0600 Subject: [PATCH 059/330] [Regression Test] Deploy memory bank test cases to CI --- .travis/basic_reg_test.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 5ffbcf6b2..c10ae3a66 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -28,7 +28,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/c echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; From 83971bba41021b8f69ac4ff37fa49e65241b3ed8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:31:31 -0600 Subject: [PATCH 060/330] [Architecture] Update cell ports for native SRAM cell --- openfpga_flow/VerilogNetlists/sram.v | 34 +++++++++---------- .../k4_N4_40nm_bank_openfpga.xml | 15 ++++---- 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 847e1a90a..8cd50c46e 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -1,31 +1,31 @@ //----------------------------------------------------- // Design Name : sram_blwl // File Name : sram.v -// Function : A SRAM cell is is accessible -// when wl is enabled // Coder : Xifan TANG //----------------------------------------------------- -module sram_blwl( -input reset, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output + + +//----------------------------------------------------- +// Function : A SRAM cell with write enable +//----------------------------------------------------- +module SRAM( + input WE, // Word line control signal as write enable + input D, // Bit line control signal + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl or wl) + always @(WE or D) begin - if (1'b1 == reset) begin - data <= 1'b0; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -33,11 +33,11 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !out; `endif endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index 110ea66a9..45fa552d0 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -146,28 +146,27 @@ - + - - - - - + + + + - + - + From 48083d2276badd369ad8f163c6cecf40823202a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 10:32:03 -0600 Subject: [PATCH 061/330] [Regression Test] Adapt fast memory bank test case --- .../full_testbench/fast_memory_bank/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index e669edf34..05e3f475b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From 7238a2be03314bf984c1de59b570ff32ca406c5a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 11:02:01 -0600 Subject: [PATCH 062/330] [Architecture] Merge latch Verilog HDL to a unique file --- openfpga_flow/VerilogNetlists/config_latch.v | 37 --- .../VerilogNetlists/config_latch_neg_rst.v | 37 --- .../VerilogNetlists/config_latch_neg_set.v | 37 --- .../VerilogNetlists/config_latch_set.v | 37 --- .../VerilogNetlists/config_latch_set_reset.v | 41 --- openfpga_flow/VerilogNetlists/latch.v | 255 ++++++++++++++++++ 6 files changed, 255 insertions(+), 189 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/config_latch.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_rst.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_set.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_set.v delete mode 100644 openfpga_flow/VerilogNetlists/config_latch_set_reset.v create mode 100644 openfpga_flow/VerilogNetlists/latch.v diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v deleted file mode 100644 index e08ea2153..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch ( - input reset, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (reset or bl or wl) begin - if (reset) begin - q_reg <= 1'b0; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v deleted file mode 100644 index cb24769d5..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active low -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch ( - input resetb, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (resetb or wl or bl) begin - if (~resetb) begin - q_reg <= 1'b0; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v deleted file mode 100644 index 2c23a73d1..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active low -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_neg_set ( - input setb, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (setb or wl or bl) begin - if (~setb) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set.v b/openfpga_flow/VerilogNetlists/config_latch_set.v deleted file mode 100644 index 945df2377..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_set.v +++ /dev/null @@ -1,37 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Set is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_set ( - input set, // Reset input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (set or bl or wl) begin - if (set) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v deleted file mode 100644 index ad9f75322..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v +++ /dev/null @@ -1,41 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated when wl is enabled -// Reset is active high -// Set is active high -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch_set_reset ( - input reset, // Reset input - input set, // Set input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ (reset or set or bl or wl) begin - if (reset) begin - q_reg <= 1'b0; - end else if (set) begin - q_reg <= 1'b1; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/latch.v b/openfpga_flow/VerilogNetlists/latch.v new file mode 100644 index 000000000..f2b0f2f09 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/latch.v @@ -0,0 +1,255 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +//----------------------------------------------------- +module LATCH ( + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (WE or D) begin + if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +//----------------------------------------------------- +module LATCHR ( + input RST, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low reset signal +//----------------------------------------------------- +module LATCHRN ( + input RSTN, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHS ( + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SET or WE or D) begin + if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low set signal +//----------------------------------------------------- +module LATCHSN ( + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SETN or WE or D) begin + if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSR ( + input RST, // Reset signal + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or SET or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSNRN ( + input RSTN, // Reset signal + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or SETN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + From fde15c4f8842612133e24f61beac76d6bb379353 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:13:35 -0600 Subject: [PATCH 063/330] [Regression Test] Add test for fast memory bank configuration using set signals --- .../fast_memory_bank_use_set/config/task.conf | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..44494baf6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 2add0406a7339a8f93e872592d27f06c435d006a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:14:03 -0600 Subject: [PATCH 064/330] [Architecture] Update architecture files for new latch naming --- .../k4_N4_40nm_frame_openfpga.xml | 15 +++++++------- ...40nm_frame_use_both_set_reset_openfpga.xml | 18 ++++++++--------- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_frame_use_set_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 16 +++++++-------- .../k4_N4_40nm_powergate_frame_openfpga.xml | 16 +++++++-------- ...4_no_local_routing_40nm_frame_openfpga.xml | 16 +++++++-------- ...tern_local_routing_40nm_frame_openfpga.xml | 16 +++++++-------- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 18 ++++++++--------- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 18 ++++++++--------- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 20 +++++++++---------- 11 files changed, 92 insertions(+), 93 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index b370c1f3d..681c67cae 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -146,28 +146,27 @@ - + - - - - - + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 2b695027a..298b49e30 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -146,29 +146,29 @@ - + - - - - - - + + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index f1894c9a5..1866e8ec1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index 96073d685..e92172048 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 0a08f0b83..c2001aa5e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 402331b6f..37292c40e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -152,28 +152,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index c579e4f49..2f6a960d1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 7ca1ba958..d0b63dd2b 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 45d660d95..118f082b4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -207,7 +207,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 6a3aba09e..4e9e16e79 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -207,7 +207,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 0cd86c659..5124e11a1 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -161,25 +161,25 @@ - + - + - - - - - + + + + + - + @@ -213,11 +213,11 @@ - + - + From 539bb617f99c72ccca3687d3d21c3c985e99b582 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:17:18 -0600 Subject: [PATCH 065/330] [Architecture] Add reset test case for frame based configuration --- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 199 ++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml new file mode 100644 index 000000000..5ee20c2e1 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From ffd1a72d22a73d6e48584d0d45d4321bd51350ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:18:26 -0600 Subject: [PATCH 066/330] [Architecture] Add regression tests for the frame-based configuration using reset and set signals --- .../config/task.conf | 42 +++++++++++++++++++ .../config/task.conf | 42 +++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf new file mode 100644 index 000000000..b5e82f32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..1f2a9bd45 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 9d9cf6ee71c21325517a034b0edae0f6ac8584cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:20:18 -0600 Subject: [PATCH 067/330] [Regression Test] Deploy new tests to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index c10ae3a66..d326e03a6 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -22,7 +22,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_c python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs @@ -33,6 +35,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs From 1b13e8ecb1b4bd2e34c398e20ea35bb7e33435c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 12:26:13 -0600 Subject: [PATCH 068/330] [Architecture] Bug fix in the SRAM Verilog --- openfpga_flow/VerilogNetlists/sram.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index 8cd50c46e..86f3ddf99 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -37,7 +37,7 @@ module SRAM( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -79,7 +79,7 @@ module SRAMS( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -121,7 +121,7 @@ module SRAMSN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -163,7 +163,7 @@ module SRAMR( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -205,7 +205,7 @@ module SRAMRN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -251,7 +251,7 @@ module SRAMSR( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule @@ -297,7 +297,7 @@ module SRAMSNRN( assign QN = ~data; `else assign Q = 1'bZ; - assign QN = !out; + assign QN = !Q; `endif endmodule From e832d806c728fea56aa99cc238693da745d0fa9f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:50:59 -0600 Subject: [PATCH 069/330] [Architecture] Add DFF Verilog netlist using standard naming convention --- openfpga_flow/VerilogNetlists/dff.v | 247 ++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/dff.v diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v new file mode 100644 index 000000000..2314cae0f --- /dev/null +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -0,0 +1,247 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flops +// File Name : ff.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A native D-type flip-flop +//----------------------------------------------------- +module DFF ( + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK) + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +//----------------------------------------------------- +module DFFR ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low reset +//----------------------------------------------------- +module DFFRN ( + input RSTN, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge RSTN) +if (~RSTN) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high set +//----------------------------------------------------- +module DFFS ( + input SET, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge SET) +if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low set +//----------------------------------------------------- +module DFFSN ( + input SETN, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge SETN) +if (~SETN) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSR ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input SE, // Scan-chain Enable + input SI, // Scan-chain input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module From e7906899ddabd68ef7e2c3277b3b4b2cdc6cf04c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:53:12 -0600 Subject: [PATCH 070/330] [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset --- .../full_testbench/fast_configuration_frame/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf index 3626d3e85..0ab4871ca 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From efad0402c2df041fba13eb2d2332063307b0c5d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 13:55:41 -0600 Subject: [PATCH 071/330] [Regression Test] Bug fix for CI errors --- .../load_external_architecture_bitstream/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf index 89ba177b6..f88536f37 100644 --- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml openfpga_vpr_device_layout=2x2 From 98d88dc68647c32b1beebb1aebb02c747eba33df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:13:48 -0600 Subject: [PATCH 072/330] [Architecture] Bug fix for vanilla memory organization --- .../k4_N4_40nm_standalone_openfpga.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 0781e6caa..43dd1e3f1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -146,28 +146,28 @@ - + - - - - - + + + + + - + - + From 178afb3c7f68c8453b10ad30e8e8cbfa36afb360 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:23:27 -0600 Subject: [PATCH 073/330] [Architecture] Add configuration chain architectures using different DFF cells --- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 11 +- ...N4_40nm_cc_use_both_set_reset_openfpga.xml | 191 ++++++++++++++++++ .../k4_N4_40nm_cc_use_reset_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_set_openfpga.xml | 190 +++++++++++++++++ .../k4_N4_40nm_cc_use_setb_openfpga.xml | 190 +++++++++++++++++ 6 files changed, 956 insertions(+), 6 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index f1db02ad1..acf0311f1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -137,28 +137,27 @@ - + - - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..e6f35ab03 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml new file mode 100644 index 000000000..6554e98a0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml new file mode 100644 index 000000000..bd18bffce --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml new file mode 100644 index 000000000..290c36e9c --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml new file mode 100644 index 000000000..1700117d9 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7fbccdd1026fe35af8bccdc83b16546299ac7c28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:34:12 -0600 Subject: [PATCH 074/330] [Regression Tests] Add test cases for configuration chain using different DFF cells --- .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../config/task.conf | 34 +++++++++++++++ .../fast_configuration_chain/config/task.conf | 3 +- .../config/task.conf | 42 +++++++++++++++++++ .../config/task.conf | 34 +++++++++++++++ 7 files changed, 213 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf new file mode 100644 index 000000000..b96d8f648 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf new file mode 100644 index 000000000..379ae0404 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..6c7ae7c75 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf new file mode 100644 index 000000000..4a8222d91 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf index 0d98afa11..04e7fef1b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf @@ -8,7 +8,6 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false @@ -18,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..d3879a68f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf new file mode 100644 index 000000000..fb8de2067 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 08838c4957fad72cfcd8c55b4a3a9921bfd17186 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:36:39 -0600 Subject: [PATCH 075/330] [Regression Test] Deploy new configuration chain test cases to CI --- .travis/basic_reg_test.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index d326e03a6..2eb3da47a 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -12,7 +12,13 @@ echo -e "Basic regression tests"; echo -e "Testing configuration chain of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From 3b42fe94d6d3bc5cdb45896b4b1322e3309504df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:41:44 -0600 Subject: [PATCH 076/330] [Architecture] Update external bitstream file --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 338 +++++++++--------- 1 file changed, 169 insertions(+), 169 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index f1f0a7362..7b6e5d3cd 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Mon Jul 27 15:47:36 2020 + - Date: Thu Sep 24 14:40:51 2020 --> @@ -11,7 +11,7 @@ - + @@ -19,7 +19,7 @@ - + @@ -64,7 +64,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -117,7 +117,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -170,7 +170,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -571,7 +571,7 @@ - + @@ -616,7 +616,7 @@ - + @@ -624,7 +624,7 @@ - + @@ -669,7 +669,7 @@ - + @@ -677,7 +677,7 @@ - + @@ -722,7 +722,7 @@ - + @@ -730,7 +730,7 @@ - + @@ -1115,7 +1115,7 @@ - + @@ -1123,7 +1123,7 @@ - + @@ -1168,7 +1168,7 @@ - + @@ -1176,7 +1176,7 @@ - + @@ -1221,7 +1221,7 @@ - + @@ -1229,7 +1229,7 @@ - + @@ -1274,7 +1274,7 @@ - + @@ -1282,24 +1282,24 @@ - + - + - + - + - - + + - + - + - + @@ -1703,7 +1703,7 @@ - + @@ -1711,7 +1711,7 @@ - + @@ -1756,7 +1756,7 @@ - + @@ -1764,7 +1764,7 @@ - + @@ -1809,7 +1809,7 @@ - + @@ -1817,7 +1817,7 @@ - + @@ -1862,7 +1862,7 @@ - + @@ -1870,7 +1870,7 @@ - + @@ -2253,13 +2253,13 @@ - + - + @@ -2269,13 +2269,13 @@ - + - + @@ -2285,13 +2285,13 @@ - + - + @@ -2301,13 +2301,13 @@ - + - + @@ -2317,13 +2317,13 @@ - + - + @@ -2333,13 +2333,13 @@ - + - + @@ -2349,13 +2349,13 @@ - + - + @@ -2365,13 +2365,13 @@ - + - + @@ -2383,13 +2383,13 @@ - + - + @@ -2399,13 +2399,13 @@ - + - + @@ -2415,13 +2415,13 @@ - + - + @@ -2431,13 +2431,13 @@ - + - + @@ -2447,13 +2447,13 @@ - + - + @@ -2463,13 +2463,13 @@ - + - + @@ -2479,13 +2479,13 @@ - + - + @@ -2495,13 +2495,13 @@ - + - + @@ -2513,13 +2513,13 @@ - + - + @@ -2529,13 +2529,13 @@ - + - + @@ -2545,13 +2545,13 @@ - + - + @@ -2561,13 +2561,13 @@ - + - + @@ -2577,13 +2577,13 @@ - + - + @@ -2593,13 +2593,13 @@ - + - + @@ -2609,13 +2609,13 @@ - + - + @@ -2625,13 +2625,13 @@ - + - + @@ -2643,13 +2643,13 @@ - + - + @@ -2659,13 +2659,13 @@ - + - + @@ -2675,13 +2675,13 @@ - + - + @@ -2691,13 +2691,13 @@ - + - + @@ -2707,13 +2707,13 @@ - + - + @@ -2723,13 +2723,13 @@ - + - + @@ -2739,13 +2739,13 @@ - + - + @@ -2755,13 +2755,13 @@ - + - + @@ -2773,13 +2773,13 @@ - + - + @@ -2789,13 +2789,13 @@ - + - + @@ -2805,13 +2805,13 @@ - + - + @@ -2821,13 +2821,13 @@ - + - + @@ -2837,13 +2837,13 @@ - + - + @@ -2853,13 +2853,13 @@ - + - + @@ -2869,13 +2869,13 @@ - + - + @@ -2885,13 +2885,13 @@ - + - + @@ -2903,13 +2903,13 @@ - + - + @@ -2919,13 +2919,13 @@ - + - + @@ -2935,13 +2935,13 @@ - + - + @@ -2951,13 +2951,13 @@ - + - + @@ -2967,13 +2967,13 @@ - + - + @@ -2983,13 +2983,13 @@ - + - + @@ -2999,13 +2999,13 @@ - + - + @@ -3015,13 +3015,13 @@ - + - + @@ -3033,13 +3033,13 @@ - + - + @@ -3049,13 +3049,13 @@ - + - + @@ -3065,13 +3065,13 @@ - + - + @@ -3081,13 +3081,13 @@ - + - + @@ -3097,13 +3097,13 @@ - + - + @@ -3113,13 +3113,13 @@ - + - + @@ -3129,13 +3129,13 @@ - + - + @@ -3145,13 +3145,13 @@ - + - + @@ -3163,13 +3163,13 @@ - + - + @@ -3179,13 +3179,13 @@ - + - + @@ -3195,13 +3195,13 @@ - + - + @@ -3211,13 +3211,13 @@ - + - + @@ -3227,13 +3227,13 @@ - + - + @@ -3243,13 +3243,13 @@ - + - + @@ -3259,13 +3259,13 @@ - + - + @@ -3275,13 +3275,13 @@ - + - + From 81965e75f6a9f71061ea8178a8cf405ba0ae1138 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 14:53:21 -0600 Subject: [PATCH 077/330] [Architecture] Bug fix in DFF Verilog HDL --- openfpga_flow/VerilogNetlists/dff.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 2314cae0f..5a8fcb8c2 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -17,7 +17,7 @@ module DFF ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge CK) +always @ (posedge CK) begin q_reg <= D; end From 9cb67e6097d2d75e64be2718d2aa1ceea5bccb63 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 15:19:37 -0600 Subject: [PATCH 078/330] [Architecture] Now all the configuration chain architecture use the DFFR cell by default --- .../k4_N4_40nm_fixed_sim_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_ccff_openfpga.xml | 6 +++--- .../k4_frac_N4_40nm_cc_openfpga.xml | 14 +++++++------- ...k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 14 +++++++------- .../openfpga_arch/k6_N10_40nm_openfpga.xml | 12 ++++++------ ...6_N10_intermediate_buffer_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 14 +++++++------- ...in_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 18 +++++++++--------- ...ac_N10_adder_chain_mem16K_40nm_openfpga.xml | 14 +++++++------- ...10_adder_chain_mem16K_aib_40nm_openfpga.xml | 14 +++++++------- ...ac_N10_adder_column_chain_40nm_openfpga.xml | 14 +++++++------- ..._N10_adder_register_chain_40nm_openfpga.xml | 14 +++++++------- ...adder_register_scan_chain_40nm_openfpga.xml | 14 +++++++------- ...gister_scan_chain_depop50_40nm_openfpga.xml | 14 +++++++------- ...scan_chain_depop50_spypad_40nm_openfpga.xml | 16 ++++++++-------- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 14 +++++++------- ...k6_frac_N10_local_encoder_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_spyio_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 14 +++++++------- .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 14 +++++++------- ...k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 14 +++++++------- ...6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 14 +++++++------- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 14 +++++++------- 28 files changed, 192 insertions(+), 192 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index 95359f565..dafbe687c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -146,28 +146,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index f6313bc22..176316e56 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,7 +146,7 @@ - + @@ -161,13 +161,13 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index ee5c4df5f..3e7ed7b81 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 7033f1eda..44dffdef3 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -161,25 +161,25 @@ - + - + - + - - + + - + @@ -195,7 +195,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 81e60ee3a..f660718ed 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -146,28 +146,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index 06ef4506d..e6abb5517 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -147,28 +147,28 @@ - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index ae4e5d1e1..5b32cd890 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 6d5df7467..33d440fa3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 6ddb0d681..e61e0666c 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -202,7 +202,7 @@ - + @@ -218,11 +218,11 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index b8c99a382..0f0437c96 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -208,7 +208,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index c0c1aa581..f29657610 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -218,7 +218,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 26af034f5..b881e140f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index e10c12d27..081b6c7a8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -162,25 +162,25 @@ - + - + - + - - + + - + @@ -196,7 +196,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 8537cfc18..d892db3ad 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -167,25 +167,25 @@ - + - + - + - - + + - + @@ -201,7 +201,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index b815842e7..01c4db307 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -167,25 +167,25 @@ - + - + - + - - + + - + @@ -201,7 +201,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index c74625e33..ec6ce1b0e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -167,7 +167,7 @@ - + @@ -182,25 +182,25 @@ - + - + - + - - + + - + @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index e4a721acb..6d1244fc4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 51e8fca53..83849f927 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9ce18bc81..ad7e28916 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -161,18 +161,18 @@ - + - + - + - - + + @@ -183,13 +183,13 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index cfda3061f..e134efbde 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -153,31 +153,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index e8980c6c3..a89ef925f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -152,31 +152,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 74d1d9933..0dc25624d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index b0c8c6ba0..cb84da0f3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index 1cb12f465..879b54a07 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 721fb6663..2136f24a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 07b4e93d8..18abbc824 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -161,31 +161,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index da7c4b76b..a1a3de80b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -153,31 +153,31 @@ - + - + - + - - + + - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index b39c7a999..a5b266d3e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -152,31 +152,31 @@ - + - + - + - - + + - + - + From 79875d5a91c68f4e975dcef42b1eb2896b05b1fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 15:27:26 -0600 Subject: [PATCH 079/330] [Architecture] Bug fix in the configuration chain arch using both reset and set --- .../k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index e6f35ab03..9014b991b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -141,8 +141,8 @@ - - + + From 8468f25b238401daaf020c926f00674ace33453a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:31:55 -0600 Subject: [PATCH 080/330] [OpenFPGA Tool] Bug fix in the smart fast configuration strategy --- .../fpga_verilog/verilog_top_testbench.cpp | 185 +++++++++++++----- 1 file changed, 135 insertions(+), 50 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index e76c198e9..c4250bdcc 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -60,6 +60,54 @@ constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg"; constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb"; +/******************************************************************** + * Identify global reset ports for programming + *******************************************************************/ +static +std::vector find_global_programming_reset_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global reset ports for programming */ + std::vector global_prog_reset_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { + global_prog_reset_ports.push_back(global_port); + } + } + + return global_prog_reset_ports; +} + +/******************************************************************** + * Identify global set ports for programming + *******************************************************************/ +static +std::vector find_global_programming_set_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global set ports for programming */ + std::vector global_prog_set_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_set(global_port)) { + global_prog_set_ports.push_back(global_port); + } + } + + return global_prog_set_ports; +} + /******************************************************************** * Print local wires for flatten memory (standalone) configuration protocols *******************************************************************/ @@ -242,7 +290,9 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { + const std::vector& global_ports, + const bool& active_global_prog_reset, + const bool& active_global_prog_set) { /* Validate the file stream */ valid_file_stream(fp); @@ -324,10 +374,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming reset port, we will active only when specified */ BasicPort stimuli_reset_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_reset_port.set_name(std::string(TOP_TB_PROG_RESET_PORT_NAME)); stimuli_reset_port.set_width(1); + activate = active_global_prog_reset; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME)); @@ -337,9 +390,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_reset_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_reset_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* Connect global set ports to operating or programming set signal */ @@ -366,10 +425,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming set port, we will active only when specified */ BasicPort stimuli_set_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_set_port.set_name(std::string(TOP_TB_PROG_SET_PORT_NAME)); stimuli_set_port.set_width(1); + activate = active_global_prog_set; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_set_port.set_name(std::string(TOP_TB_SET_PORT_NAME)); @@ -379,9 +441,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_set_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_set_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* For the rest of global ports, wire them to constant signals */ @@ -584,6 +652,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, static size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits(); @@ -602,7 +671,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; size_t num_bits_to_skip = 0; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { break; } num_bits_to_skip++; @@ -623,7 +692,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; num_config_clock_cycles = 1; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == fabric_bitstream.bit_din(bit_id)) { + if (bit_value_to_skip != fabric_bitstream.bit_din(bit_id)) { num_config_clock_cycles++; } } @@ -1008,11 +1077,11 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, fp << std::endl; /* Programming set signal for configuration circuit : always disabled */ - print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- Begin programming set signal generation -----"); print_verilog_pulse_stimuli(fp, prog_set_port, - 0, /* Initial value */ + 1, /* Initial value */ prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- End programming set signal generation -----"); fp << std::endl; @@ -1526,41 +1595,11 @@ static void print_verilog_top_testbench_bitstream(std::fstream& fp, const e_config_protocol_type& config_protocol_type, const bool& fast_configuration, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { - /* Try to find global reset/set ports for programming */ - std::vector global_prog_reset_ports; - std::vector global_prog_set_ports; - for (const CircuitPortId& global_port : global_ports) { - VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); - if (false == circuit_lib.port_is_prog(global_port)) { - continue; - } - VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); - VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) - || (false == circuit_lib.port_is_set(global_port))); - if (true == circuit_lib.port_is_reset(global_port)) { - global_prog_reset_ports.push_back(global_port); - } - if (true == circuit_lib.port_is_set(global_port)) { - global_prog_set_ports.push_back(global_port); - } - } - - bool apply_fast_configuration = fast_configuration; - if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) - && (true == fast_configuration)) { - VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); - } - bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol_type, - apply_fast_configuration, - global_prog_reset_ports, - global_prog_set_ports, - bitstream_manager, fabric_bitstream); /* Branch on the type of configuration protocol */ switch (config_protocol_type) { @@ -1570,18 +1609,18 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, bit_value_to_skip, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_memory_bank_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_bitstream(fp, apply_fast_configuration, + print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, bit_value_to_skip, module_manager, top_module, fabric_bitstream); @@ -1652,6 +1691,23 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Preparation: find all the clock ports */ std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); + /* Preparation: find all the reset/set ports for programming usage */ + std::vector global_prog_reset_ports = find_global_programming_reset_ports(circuit_lib, global_ports); + std::vector global_prog_set_ports = find_global_programming_set_ports(circuit_lib, global_ports); + + /* Identify if we can apply fast configuration */ + bool apply_fast_configuration = fast_configuration; + if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) + && (true == fast_configuration)) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); + apply_fast_configuration = false; + } + bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), + apply_fast_configuration, + global_prog_reset_ports, + global_prog_set_ports, + bitstream_manager, fabric_bitstream); + /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, @@ -1663,7 +1719,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, float op_clock_period = (1./simulation_parameters.operating_clock_frequency()); /* Estimate the number of configuration clock cycles */ size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(), - fast_configuration, + apply_fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); @@ -1674,10 +1731,38 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, op_clock_period, VERILOG_SIM_TIMESCALE); + /* Identify the stimulus for global reset/set for programming purpose: + * - If only reset port is seen we turn on Reset + * - If only set port is seen we turn on Reset + * - If both reset and set port is defined, + * we pick the one which is consistent with the bit value to be skipped + */ + bool active_global_prog_reset = false; + bool active_global_prog_set = false; + + if (!global_prog_reset_ports.empty()) { + active_global_prog_reset = true; + } + + if (!global_prog_set_ports.empty()) { + active_global_prog_set = true; + } + + /* Ensure that at most only one of the two switches is activated */ + if ( (true == active_global_prog_reset) + && (true == active_global_prog_set) ) { + /* If we will skip logic '0', we will activate programming reset */ + active_global_prog_reset = !bit_value_to_skip; + /* If we will skip logic '1', we will activate programming set */ + active_global_prog_set = bit_value_to_skip; + } + /* Generate stimuli for global ports or connect them to existed signals */ print_verilog_top_testbench_global_ports_stimuli(fp, module_manager, top_module, - circuit_lib, global_ports); + circuit_lib, global_ports, + active_global_prog_reset, + active_global_prog_set); /* Instanciate FPGA top-level module */ print_verilog_testbench_fpga_instance(fp, module_manager, top_module, @@ -1706,8 +1791,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* load bitstream to FPGA fabric in a configuration phase */ print_verilog_top_testbench_bitstream(fp, config_protocol.type(), - fast_configuration, - circuit_lib, global_ports, + apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, bitstream_manager, fabric_bitstream); From 4d94fcb2982935f65a387ab662fd712659ed01d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:38:34 -0600 Subject: [PATCH 081/330] [Regression Test] Bug fix in calling test cases --- .travis/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 2eb3da47a..53dd98393 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -18,7 +18,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From fc154b8560a2f30c44b4e6bc1d3c659106069c54 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:45:56 -0600 Subject: [PATCH 082/330] [Architecture] Bug fix due to switching CCFF cell --- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 176316e56..ca630da7e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -146,15 +146,15 @@ - + - + - + - + From 2d81ff90121b9984f9e022ec7133b33a510e0554 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 16:59:52 -0600 Subject: [PATCH 083/330] [Regression test] Add configuration chain test case where both set and reset are used --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf new file mode 100644 index 000000000..288a3564a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 335f5b78c12c7495e86e8505bc930d01a6f98430 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:02:28 -0600 Subject: [PATCH 084/330] [Regression Test] Add test case to use both set and reset for configuration frame --- .../config/task.conf | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf new file mode 100644 index 000000000..548e37cb8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 19dd3778d9a5a0237350751d9bd851f113d63be9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:04:24 -0600 Subject: [PATCH 085/330] [Architecture] Add test case for memory bank to use both reset and set --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf new file mode 100644 index 000000000..855e3156e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From a30255b2a441e92c70ec1b7f347e714010de2cae Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:04:43 -0600 Subject: [PATCH 086/330] [Regression Test] Deploy new test cases to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 53dd98393..f84af4b37 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -16,6 +16,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs @@ -32,6 +33,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; @@ -40,6 +42,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs From 0a5369f919a4e0fd9ebdae51213ce6f47e8d2851 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:26:48 -0600 Subject: [PATCH 087/330] [Architecture] Adapt all the architecture files to use standard DFF cell --- openfpga_flow/VerilogNetlists/dff.v | 34 +++++++++++++++++++ .../k4_N4_40nm_bank_openfpga.xml | 14 ++++---- ..._40nm_bank_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 10 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 10 +++--- ...N4_40nm_cc_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_cc_use_setb_openfpga.xml | 10 +++--- .../k4_N4_40nm_fixed_sim_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_ccff_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_scff_openfpga.xml | 10 +++--- ...40nm_frame_use_both_set_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_set_openfpga.xml | 10 +++--- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 10 +++--- .../k4_N4_40nm_powergate_frame_openfpga.xml | 10 +++--- .../k4_N4_40nm_standalone_openfpga.xml | 10 +++--- ...4_no_local_routing_40nm_frame_openfpga.xml | 10 +++--- ...tern_local_routing_40nm_frame_openfpga.xml | 10 +++--- .../k4_frac_N4_40nm_cc_openfpga.xml | 10 +++--- ...4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 10 +++--- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 12 +++---- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 12 +++---- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 +++---- .../openfpga_arch/k6_N10_40nm_openfpga.xml | 10 +++--- ..._N10_intermediate_buffer_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 10 +++--- ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 +++---- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 12 +++---- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 +++---- ...c_N10_adder_column_chain_40nm_openfpga.xml | 10 +++--- ...N10_adder_register_chain_40nm_openfpga.xml | 10 +++--- ...dder_register_scan_chain_40nm_openfpga.xml | 8 ++--- ...ister_scan_chain_depop50_40nm_openfpga.xml | 8 ++--- ...can_chain_depop50_spypad_40nm_openfpga.xml | 8 ++--- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 10 +++--- ...6_frac_N10_local_encoder_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_spyio_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 10 +++--- ...6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 10 +++--- ...k6_frac_N8_local_encoder_40nm_openfpga.xml | 10 +++--- ..._frac_N8_outbuf_only_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 10 +++--- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 10 +++--- 55 files changed, 309 insertions(+), 275 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 5a8fcb8c2..25701e694 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -203,6 +203,40 @@ end endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSRQ ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; +`else + assign Q = 1'bZ; +`endif + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index 45fa552d0..fd4379b60 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -124,15 +124,15 @@ - + - - - - - + + + + + @@ -192,7 +192,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index 95c93a6db..7a03fcefd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 33581d64a..349d71e0d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index 184c5b14c..2c0705f83 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index 904ee811a..296593272 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index 68a29312a..69267a999 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index acf0311f1..b137b5f74 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -183,7 +183,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 9014b991b..566fb305d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -185,7 +185,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index 6554e98a0..85787e154 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index bd18bffce..95f33581c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 290c36e9c..1e0a9a422 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index 1700117d9..23ba4e1f3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index dafbe687c..e9ccfdbe5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index ca630da7e..0419f0f3d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index 681c67cae..a21fa751c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -192,7 +192,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 7ccada510..ccaa8b66c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -195,7 +195,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 298b49e30..e6f401309 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 5ee20c2e1..449ed1740 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index 1866e8ec1..e2f838905 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index e92172048..a2315d5a1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index c2001aa5e..20189c8a5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 37292c40e..118a12b5a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 43dd1e3f1..0d9a0e85d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 2f6a960d1..24a296aa3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index d0b63dd2b..aa04235c4 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -206,7 +206,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 3e7ed7b81..61280345a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 44dffdef3..70896f503 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -225,7 +225,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 118f082b4..20a91779d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 4e9e16e79..89eb8d37f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -241,7 +241,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 5124e11a1..6dffbfd2c 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + @@ -247,7 +247,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index f660718ed..1f6370321 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index e6abb5517..750ff9fac 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 5b32cd890..6dc828cc6 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 33d440fa3..6c30d6381 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index e61e0666c..937dd27f1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -216,7 +216,7 @@ - + @@ -252,7 +252,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 0f0437c96..12117aad3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + @@ -238,7 +238,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index f29657610..f3a821c95 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + @@ -250,7 +250,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index b881e140f..2253f034d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 081b6c7a8..63c47f5d6 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index d892db3ad..9d1185882 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 01c4db307..3303e65b8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index ec6ce1b0e..df6418450 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index 6d1244fc4..6fb6bc2c8 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 83849f927..75387fa12 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index ad7e28916..9d8a77ee4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index e134efbde..1aa072294 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index a89ef925f..d2e505db0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 0dc25624d..fee0b0f2d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index cb84da0f3..ab2309ec1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index 879b54a07..dd13e5003 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 2136f24a1..8ce4a01a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 18abbc824..395a166f0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index a1a3de80b..2821a6f36 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index a5b266d3e..d7bf58889 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -203,7 +203,7 @@ - + From 49d6863641909c2f13f4c7d5f82c1a9281f8b602 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:33:14 -0600 Subject: [PATCH 088/330] [Architecture] Bug fix for scan-chain FF cell renaming --- openfpga_flow/VerilogNetlists/dff.v | 9 +++------ ...rac_N10_adder_register_scan_chain_40nm_openfpga.xml | 8 ++++---- ...adder_register_scan_chain_depop50_40nm_openfpga.xml | 6 +++--- ...egister_scan_chain_depop50_spypad_40nm_openfpga.xml | 10 +++++----- 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 25701e694..3e767d8c4 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -244,15 +244,14 @@ endmodule //End Of Module // - scan-chain input // - a scan-chain enable //----------------------------------------------------- -module SDFFSR ( +module SDFFSRQ ( input SET, // Set input input RST, // Reset input - input SE, // Scan-chain Enable - input SI, // Scan-chain input input CK, // Clock Input + input SE, // Scan-chain Enable input D, // Data Input + input SI, // Scan-chain input output Q, // Q output - output QN // QB output ); //------------Internal Variables-------- reg q_reg; @@ -272,10 +271,8 @@ end `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q assign Q = q_reg; - assign QN = ~q_reg; `else assign Q = 1'bZ; - assign QN = !Q; `endif endmodule //End Of Module diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 9d1185882..41867db36 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - + + @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 3303e65b8..1aa06737b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index df6418450..f288f47ef 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,13 +142,13 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - + @@ -243,7 +243,7 @@ - + @@ -278,7 +278,7 @@ - + @@ -311,7 +311,7 @@ - + From 54b3f244d3bddefb3c2c26ac9d08c9f60dc480f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:35:02 -0600 Subject: [PATCH 089/330] [Architecture] Remove obsolete Verilog netlists --- openfpga_flow/VerilogNetlists/ff.v | 146 -------------------------- openfpga_flow/VerilogNetlists/ff_en.v | 40 ------- 2 files changed, 186 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/ff.v delete mode 100644 openfpga_flow/VerilogNetlists/ff_en.v diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v deleted file mode 100644 index 2f2477f24..000000000 --- a/openfpga_flow/VerilogNetlists/ff.v +++ /dev/null @@ -1,146 +0,0 @@ -//----------------------------------------------------- -// Design Name : static_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//------ Include defines: preproc flags ----- -// `include "./SRC/fpga_defines.v" -module static_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - -module scan_chain_ff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -input TESTEN, // Clock Input -/* Local ports follow */ -input D, // Data Input -input DI, // Scan Chain Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else if (TESTEN) begin - q_reg <= DI; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - - -//----------------------------------------------------- -// Design Name : scan_chain_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; - -endmodule //End Of Module static_dff - -//----------------------------------------------------- -// Design Name : scan_chain_dff compact -// File Name : ff.v -// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff_compact ( -/* Global ports go first */ -input reset, // Reset input -//input set, // set input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset /*or posedge set*/) -if (reset) begin - q_reg <= 1'b0; -//end else if (set) begin -// q_reg <= 1'b1; -end else begin - q_reg <= D; -end -/* -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; -*/ - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule //End Of Module static_dff diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v deleted file mode 100644 index 11b657a9f..000000000 --- a/openfpga_flow/VerilogNetlists/ff_en.v +++ /dev/null @@ -1,40 +0,0 @@ -//----------------------------------------------------- -// Design Name : D-type Flip-flop with Write Enable -// File Name : ff_en.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module DFF_EN ( -/* Global ports go first */ -input SET, // set input -input RST, // Reset input -input WE, // Write Enable -input CK, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output QB // QB output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge CK or posedge RST or posedge SET) -if (RST) begin - q_reg <= 1'b0; -end else if (SET) begin - q_reg <= 1'b1; -end else if (WE) begin - q_reg <= D; -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign QB = ~q_reg; -`else -assign Q = 1'bZ; -assign QB = !Q; -`endif - -endmodule //End Of Module From 749455631670ccea28c5da4a9905e14d9a9dfd3f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:38:16 -0600 Subject: [PATCH 090/330] [Architecture] Bug fix for scan-chain FF cell --- openfpga_flow/VerilogNetlists/dff.v | 43 +++++++++++++++++++ .../k4_N4_40nm_frame_scff_openfpga.xml | 7 +-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 3e767d8c4..6f62e627c 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -237,6 +237,49 @@ end endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q + assign Q = q_reg; + assign QN = !Q; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index ccaa8b66c..3ed8a652b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -146,17 +146,18 @@ - + - + - + + From 3e7c88eac85091de439ac3152540eddfaa6eebf6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:41:03 -0600 Subject: [PATCH 091/330] [Architecture] Bug fix in Verilog netlist for scan-chain DFF --- openfpga_flow/VerilogNetlists/dff.v | 4 ++-- .../openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 6f62e627c..6ed1428d4 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -213,7 +213,7 @@ module DFFSRQ ( input RST, // Reset input input CK, // Clock Input input D, // Data Input - output Q, // Q output + output Q // Q output ); //------------Internal Variables-------- reg q_reg; @@ -294,7 +294,7 @@ module SDFFSRQ ( input SE, // Scan-chain Enable input D, // Data Input input SI, // Scan-chain input - output Q, // Q output + output Q // Q output ); //------------Internal Variables-------- reg q_reg; diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 3ed8a652b..53b5e2ebd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -155,7 +155,7 @@ - + @@ -164,13 +164,13 @@ - + - + From 3ade6d6ff5ba7e3118f28edf11d61b3940d5ea39 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 17:53:30 -0600 Subject: [PATCH 092/330] [Architecture] Bug fix for dff that are used in data path --- openfpga_flow/VerilogNetlists/dff.v | 14 ++------------ ...k4_N4_40nm_bank_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 6 +++--- 7 files changed, 20 insertions(+), 30 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v index 6ed1428d4..8803e1239 100644 --- a/openfpga_flow/VerilogNetlists/dff.v +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -228,12 +228,7 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -311,11 +306,6 @@ end else begin q_reg <= D; end -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index 7a03fcefd..e5ce87852 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 349d71e0d..86fc2e5fc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index 2c0705f83..c6c589f66 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index 296593272..b1b339401 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index 69267a999..d84703d52 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index b137b5f74..c119e0b9a 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -120,10 +120,10 @@ - - + + - + From d51efd397ffcfb40667d13f7b56257dd32640b98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:02:42 -0600 Subject: [PATCH 093/330] [Architecture] Bug fix for architectures using DFF cells --- openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index fd4379b60..a6b32fdd9 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -129,10 +129,10 @@ - - + + - + @@ -192,7 +192,7 @@ - + From 60a14ccbd21184ce04ce170497f0591572db42fa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:20:55 -0600 Subject: [PATCH 094/330] [Architecture] Bug fix in architectures that use BRAM --- .../k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 2 +- .../k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 2 +- ...frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 2 +- ...rac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 2 +- .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 2 +- .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 20a91779d..09fe2c681 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 89eb8d37f..79980dacc 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 6dffbfd2c..d5c6fff86 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 937dd27f1..3b1ab1732 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 12117aad3..92f56df47 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index f3a821c95..2543f9096 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -204,7 +204,7 @@ - + From eb5fd1f44eba9f7225ceb26aeb27011d31bd5cef Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 18:37:25 -0600 Subject: [PATCH 095/330] [Architecture] Bug fix for architectures using scan-chain DFF cell --- ...frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 2 +- ...0_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 1aa06737b..a3d5b3bb7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index f288f47ef..ac7547e57 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -147,7 +147,7 @@ - + From e0f9547f5b9e5c23238eb294047c3b16b9e99552 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 19:53:54 -0600 Subject: [PATCH 096/330] [Architecture] Rework the i/o cell Verilog HDL --- openfpga_flow/VerilogNetlists/gpio.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/gpio.v diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/VerilogNetlists/gpio.v new file mode 100644 index 000000000..5fb318f3d --- /dev/null +++ b/openfpga_flow/VerilogNetlists/gpio.v @@ -0,0 +1,20 @@ +//----------------------------------------------------- +// Design Name : General Purpose I/Os +// File Name : gpio.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A minimum general purpose I/O +//----------------------------------------------------- +module GPIO ( + input A, // Data output + output Y, // Data input + inout PAD, // bi-directional pad + input DIR // direction control +); + //----- when direction enabled, the signal is propagated from PAD to data input + assign Y = DIR ? PAD : 1'bz; + //----- when direction is disabled, the signal is propagated from data out to pad + assign PAD = DIR ? 1'bz : A; +endmodule From 4a0a4481710ef04f247b8e003e0cec550a451d22 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 19:56:01 -0600 Subject: [PATCH 097/330] [Architecture] Rename openfpga architecture for the I/O cell --- openfpga_flow/VerilogNetlists/io.v | 16 ---------------- .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 12 ++++++------ ..._N4_40nm_bank_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_bank_use_setb_openfpga.xml | 12 ++++++------ .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 12 ++++++------ ...k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_cc_use_setb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_fixed_sim_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_ccff_openfpga.xml | 12 ++++++------ .../openfpga_arch/k4_N4_40nm_frame_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_scff_openfpga.xml | 12 ++++++------ ...N4_40nm_frame_use_both_set_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_reset_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_set_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_frame_use_setb_openfpga.xml | 12 ++++++------ .../k4_N4_40nm_powergate_frame_openfpga.xml | 14 +++++++------- .../k4_N4_40nm_standalone_openfpga.xml | 12 ++++++------ ...4_N4_no_local_routing_40nm_frame_openfpga.xml | 12 ++++++------ ...pattern_local_routing_40nm_frame_openfpga.xml | 12 ++++++------ .../k4_frac_N4_40nm_cc_openfpga.xml | 12 ++++++------ .../k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 12 ++++++------ ..._N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 12 ++++++------ ...dder_chain_mem1K_L124_40nm_frame_openfpga.xml | 12 ++++++------ ...hain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_N10_40nm_openfpga.xml | 12 ++++++------ .../k6_N10_intermediate_buffer_40nm_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_frac_N10_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 12 ++++++------ ...hain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 ++++++------ ...frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 12 ++++++------ ..._N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 14 +++++++------- ...frac_N10_adder_column_chain_40nm_openfpga.xml | 12 ++++++------ ...ac_N10_adder_register_chain_40nm_openfpga.xml | 12 ++++++------ ...0_adder_register_scan_chain_40nm_openfpga.xml | 12 ++++++------ ...register_scan_chain_depop50_40nm_openfpga.xml | 12 ++++++------ ...r_scan_chain_depop50_spypad_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_behavioral_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_local_encoder_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_spyio_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 12 ++++++------ .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 12 ++++++------ 55 files changed, 326 insertions(+), 342 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/io.v diff --git a/openfpga_flow/VerilogNetlists/io.v b/openfpga_flow/VerilogNetlists/io.v deleted file mode 100644 index 9fccdd23d..000000000 --- a/openfpga_flow/VerilogNetlists/io.v +++ /dev/null @@ -1,16 +0,0 @@ -//------ Module: iopad -----// -//------ Verilog file: io.v -----// -//------ Author: Xifan TANG -----// -module iopad( -//input zin, // Set output to be Z -input outpad, // Data output -output inpad, // Data input -inout pad, // bi-directional pad -input en // enable signal to control direction of iopad -//input direction_inv // enable signal to control direction of iopad -); - //----- when direction enabled, the signal is propagated from pad to din - assign inpad = en ? pad : 1'bz; - //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = en ? 1'bz : outpad; -endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index a6b32fdd9..e2ce76956 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -155,14 +155,14 @@ - + - - - - + + + + @@ -180,7 +180,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index e5ce87852..d8f97ba41 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 86fc2e5fc..427889368 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index c6c589f66..d03b2d2be 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index b1b339401..fec761135 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index d84703d52..dc3c89739 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index c119e0b9a..a36a863fd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -146,14 +146,14 @@ - + - - - - + + + + @@ -171,7 +171,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 566fb305d..762fc1af3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -148,14 +148,14 @@ - + - - - - + + + + @@ -173,7 +173,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index 85787e154..c74d0aedb 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index 95f33581c..3e453fb3f 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 1e0a9a422..78461fadc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index 23ba4e1f3..ee990043b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -147,14 +147,14 @@ - + - - - - + + + + @@ -172,7 +172,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index e9ccfdbe5..dced448a2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 0419f0f3d..5d9aee9eb 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index a21fa751c..92b7930c7 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -155,14 +155,14 @@ - + - - - - + + + + @@ -180,7 +180,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index 53b5e2ebd..ff3f2e1b0 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -159,14 +159,14 @@ - + - - - - + + + + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index e6f401309..7495f9c3b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 449ed1740..0b7f14a25 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index e2f838905..f43436de5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index a2315d5a1..cee0fbc79 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 20189c8a5..7ba360992 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 118a12b5a..0d03dc6d6 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -36,7 +36,7 @@ - + @@ -162,14 +162,14 @@ - + - - - - + + + + @@ -187,7 +187,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 0d9a0e85d..3392eef23 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 24a296aa3..cf0502130 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index aa04235c4..6366425e0 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 61280345a..ceef842c0 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 70896f503..d293c206e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 09fe2c681..57ba20070 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -224,7 +224,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 79980dacc..45614dd10 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index d5c6fff86..8746805da 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 1f6370321..9c8e66a87 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -156,14 +156,14 @@ - + - - - - + + + + @@ -181,7 +181,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index 750ff9fac..e0e8cd461 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -157,14 +157,14 @@ - + - - - - + + + + @@ -182,7 +182,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 6dc828cc6..3afe5a693 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 6c30d6381..66f172080 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -213,7 +213,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 3b1ab1732..f883dc1d2 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -239,7 +239,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 92f56df47..b83c1c63a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -225,7 +225,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 2543f9096..08d2ca9ed 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -214,7 +214,7 @@ - + @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 2253f034d..1a7b74700 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -213,7 +213,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 63c47f5d6..6305544b2 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -175,14 +175,14 @@ - + - - - - + + + + @@ -214,7 +214,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 41867db36..93589b263 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -180,14 +180,14 @@ - + - - - - + + + + @@ -220,7 +220,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index a3d5b3bb7..da3e8ec60 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -180,14 +180,14 @@ - + - - - - + + + + @@ -219,7 +219,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index ac7547e57..1f07c79dc 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -195,14 +195,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index 6fb6bc2c8..a0d9be879 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 75387fa12..ef3bf9f21 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9d8a77ee4..f9fcfe148 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -174,18 +174,18 @@ - + - + - - - + + + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index 1aa072294..588e88620 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -166,14 +166,14 @@ - + - - - - + + + + @@ -191,7 +191,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index d2e505db0..da9767f10 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -165,14 +165,14 @@ - + - - - - + + + + @@ -190,7 +190,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index fee0b0f2d..098e7ba2e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index ab2309ec1..53dda3357 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index dd13e5003..f050bd8a7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 8ce4a01a1..ec3f99c4d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 395a166f0..cab4ef22b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -174,14 +174,14 @@ - + - - - - + + + + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index 2821a6f36..e367ff8bb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -166,14 +166,14 @@ - + - - - - + + + + @@ -191,7 +191,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index d7bf58889..0585bf591 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -165,14 +165,14 @@ - + - - - - + + + + @@ -190,7 +190,7 @@ - + From 53187044e6a2e22846efeacb22f90abb4da7813d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:07:57 -0600 Subject: [PATCH 098/330] [Architecture] Rename adder cell --- openfpga_flow/VerilogNetlists/adder.v | 33 ++++++++++++++------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/adder.v b/openfpga_flow/VerilogNetlists/adder.v index da288c9b9..fa13384d9 100644 --- a/openfpga_flow/VerilogNetlists/adder.v +++ b/openfpga_flow/VerilogNetlists/adder.v @@ -1,19 +1,20 @@ -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module adder( -input [0:0] a, // Input a -input [0:0] b, // Input b -input [0:0] cin, // Input cin -output [0:0] cout, // Output carry -output [0:0] sumout // Output sum -); -//wire[1:0] int_calc; +//----------------------------------------------------- +// Design Name : Multi-bit Full Adder +// File Name : adder.v +// Coder : Xifan TANG +//----------------------------------------------------- -//assign int_calc = a + b + cin; -//assign cout = int_calc[1]; -//assign sumout = int_calc[0]; - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | (a & cin) | (b & cin); +//----------------------------------------------------- +// Function : A 1-bit full adder +//----------------------------------------------------- +module ADDF( + input [0:0] A, // Input a + input [0:0] B, // Input b + input [0:0] CI, // Input cin + output [0:0] CO, // Output carry + output [0:0] SUM // Output sum +); + assign SUM = A ^ B ^ CI; + assign CO = (A & B) | (A & CI) | (B & CI); endmodule From 4ada793c84c9bb34a84295667fc60178400e582c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:09:29 -0600 Subject: [PATCH 099/330] [Architecture] Adapt openfpga architecture to follow the renamed adder cell --- ...4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 18 +++++++-------- ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 18 +++++++-------- ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 18 +++++++-------- ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 22 +++++++++---------- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 18 +++++++-------- ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 22 +++++++++---------- ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 18 +++++++-------- ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 18 +++++++-------- ...c_N10_adder_column_chain_40nm_openfpga.xml | 18 +++++++-------- ...N10_adder_register_chain_40nm_openfpga.xml | 18 +++++++-------- ...dder_register_scan_chain_40nm_openfpga.xml | 18 +++++++-------- ...ister_scan_chain_depop50_40nm_openfpga.xml | 18 +++++++-------- ...can_chain_depop50_spypad_40nm_openfpga.xml | 22 +++++++++---------- 13 files changed, 123 insertions(+), 123 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index d293c206e..114ffecad 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 57ba20070..56b3a3b0d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -238,7 +238,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 45614dd10..e44bfbff4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -242,7 +242,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 8746805da..d51bd7215 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -183,15 +183,15 @@ - + - - - - - + + + + + @@ -209,8 +209,8 @@ - - + + @@ -248,7 +248,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 66f172080..4fec07c77 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index f883dc1d2..cc50bf9ed 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,22 +184,22 @@ - + - - - - - + + + + + - - + + @@ -253,7 +253,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index b83c1c63a..e9b25c714 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -239,7 +239,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 08d2ca9ed..34474e19e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -251,7 +251,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 1a7b74700..2e82fedfc 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 6305544b2..10b8f2ba4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -184,15 +184,15 @@ - + - - - - - + + + + + @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 93589b263..4d7ba7fd0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -189,15 +189,15 @@ - + - - - - - + + + + + @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index da3e8ec60..455688737 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -189,15 +189,15 @@ - + - - - - - + + + + + @@ -229,7 +229,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 1f07c79dc..6f0b235ba 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 @@ -204,15 +204,15 @@ - + - - - - - + + + + + @@ -244,7 +244,7 @@ - + @@ -279,7 +279,7 @@ - + @@ -312,7 +312,7 @@ - + From 8edfc79f53b76751e0dc25373c5767794fe2c121 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:11:21 -0600 Subject: [PATCH 100/330] [Architecture] Rename AIB cell --- openfpga_flow/VerilogNetlists/aib.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 2ebfd5cea..86ea4f671 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -5,12 +5,12 @@ // Coder : Xifan Tang //----------------------------------------------------- -module aib ( - input tx_clk, - input rx_clk, - inout[0:79] pad, - input[0:79] tx_data, - output[0:79] rx_data); +module AIB ( + input TXCLK, + input RXCLK, + inout[0:79] PAD, + input[0:79] TXDATA, + output[0:79] RXDATA); // May add the logic function of a real AIB // Refer to the offical AIB github From bd0f0144a0724ffcfe4dd0fd514f00c077cb2750 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:14:16 -0600 Subject: [PATCH 101/330] [Architecture] Rename AIB architecture for the new cell naming --- openfpga_flow/VerilogNetlists/aib.v | 8 ++++---- ...frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 86ea4f671..8d1b9e6da 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -6,11 +6,11 @@ //----------------------------------------------------- module AIB ( - input TXCLK, - input RXCLK, + input TX_CLK, + input RX_CLK, inout[0:79] PAD, - input[0:79] TXDATA, - output[0:79] RXDATA); + input[0:79] TX_DATA, + output[0:79] RX_DATA); // May add the logic function of a real AIB // Refer to the offical AIB github diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 34474e19e..c1a7d8d3d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -206,14 +206,14 @@ - + - - - - + + + + @@ -234,7 +234,7 @@ - + From e4bfa2ef51ad54432b51f735ec4851bb2b489088 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:16:50 -0600 Subject: [PATCH 102/330] [Architecture] Update external bitstream file --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 258 +++++++++--------- 1 file changed, 129 insertions(+), 129 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index 7b6e5d3cd..07a874f86 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Thu Sep 24 14:40:51 2020 + - Date: Thu Sep 24 20:16:32 2020 --> @@ -2253,13 +2253,13 @@ - + - + @@ -2269,13 +2269,13 @@ - + - + @@ -2285,13 +2285,13 @@ - + - + @@ -2301,13 +2301,13 @@ - + - + @@ -2317,13 +2317,13 @@ - + - + @@ -2333,13 +2333,13 @@ - + - + @@ -2349,13 +2349,13 @@ - + - + @@ -2365,13 +2365,13 @@ - + - + @@ -2383,13 +2383,13 @@ - + - + @@ -2399,13 +2399,13 @@ - + - + @@ -2415,13 +2415,13 @@ - + - + @@ -2431,13 +2431,13 @@ - + - + @@ -2447,13 +2447,13 @@ - + - + @@ -2463,13 +2463,13 @@ - + - + @@ -2479,13 +2479,13 @@ - + - + @@ -2495,13 +2495,13 @@ - + - + @@ -2513,13 +2513,13 @@ - + - + @@ -2529,13 +2529,13 @@ - + - + @@ -2545,13 +2545,13 @@ - + - + @@ -2561,13 +2561,13 @@ - + - + @@ -2577,13 +2577,13 @@ - + - + @@ -2593,13 +2593,13 @@ - + - + @@ -2609,13 +2609,13 @@ - + - + @@ -2625,13 +2625,13 @@ - + - + @@ -2643,13 +2643,13 @@ - + - + @@ -2659,13 +2659,13 @@ - + - + @@ -2675,13 +2675,13 @@ - + - + @@ -2691,13 +2691,13 @@ - + - + @@ -2707,13 +2707,13 @@ - + - + @@ -2723,13 +2723,13 @@ - + - + @@ -2739,13 +2739,13 @@ - + - + @@ -2755,13 +2755,13 @@ - + - + @@ -2773,13 +2773,13 @@ - + - + @@ -2789,13 +2789,13 @@ - + - + @@ -2805,13 +2805,13 @@ - + - + @@ -2821,13 +2821,13 @@ - + - + @@ -2837,13 +2837,13 @@ - + - + @@ -2853,13 +2853,13 @@ - + - + @@ -2869,13 +2869,13 @@ - + - + @@ -2885,13 +2885,13 @@ - + - + @@ -2903,13 +2903,13 @@ - + - + @@ -2919,13 +2919,13 @@ - + - + @@ -2935,13 +2935,13 @@ - + - + @@ -2951,13 +2951,13 @@ - + - + @@ -2967,13 +2967,13 @@ - + - + @@ -2983,13 +2983,13 @@ - + - + @@ -2999,13 +2999,13 @@ - + - + @@ -3015,13 +3015,13 @@ - + - + @@ -3033,13 +3033,13 @@ - + - + @@ -3049,13 +3049,13 @@ - + - + @@ -3065,13 +3065,13 @@ - + - + @@ -3081,13 +3081,13 @@ - + - + @@ -3097,13 +3097,13 @@ - + - + @@ -3113,13 +3113,13 @@ - + - + @@ -3129,13 +3129,13 @@ - + - + @@ -3145,13 +3145,13 @@ - + - + @@ -3163,13 +3163,13 @@ - + - + @@ -3179,13 +3179,13 @@ - + - + @@ -3195,13 +3195,13 @@ - + - + @@ -3211,13 +3211,13 @@ - + - + @@ -3227,13 +3227,13 @@ - + - + @@ -3243,13 +3243,13 @@ - + - + @@ -3259,13 +3259,13 @@ - + - + @@ -3275,13 +3275,13 @@ - + - + From 0a53a719bdab86936b717cf6958dea7b7f04d65f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:42:24 -0600 Subject: [PATCH 103/330] [Architecture] Bug fix due to adder renaming --- .../openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 4 ++-- .../k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 4 ++-- .../k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 4 ++-- ...ac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 4 ++-- .../openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml | 4 ++-- ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_register_chain_40nm_openfpga.xml | 4 ++-- .../k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml | 4 ++-- ...ac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 4 ++-- ...adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 4 ++-- 13 files changed, 26 insertions(+), 26 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 114ffecad..beeb811e1 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 56b3a3b0d..aed95c588 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index e44bfbff4..f5efbc285 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index d51bd7215..3a53d9aa4 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 4fec07c77..adc3da01e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index cc50bf9ed..1b2d8ffcb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index e9b25c714..2733b0317 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index c1a7d8d3d..d900f0edb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 2e82fedfc..b5439a151 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 10b8f2ba4..b22057acb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 4d7ba7fd0..748f8ec48 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 455688737..4335c3ae4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 6f0b235ba..765bd94a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -69,8 +69,8 @@ - - + + 10e-12 5e-12 From 00bf775971132343be5aa5857a8c73641a5dea5b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 20:54:18 -0600 Subject: [PATCH 104/330] [Architecture] Bug fix for adder renaming --- ...ac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 3a53d9aa4..af193a385 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -209,8 +209,8 @@ - - + + From 20d6b2bf84fd971295149a45260d2ac7e7475d24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 21:14:13 -0600 Subject: [PATCH 105/330] [Architecture] Remove out-of-date Verilog testbench --- openfpga_flow/VerilogNetlists/lb_tb.v | 199 -------------------------- 1 file changed, 199 deletions(-) delete mode 100644 openfpga_flow/VerilogNetlists/lb_tb.v diff --git a/openfpga_flow/VerilogNetlists/lb_tb.v b/openfpga_flow/VerilogNetlists/lb_tb.v deleted file mode 100644 index 705970fd6..000000000 --- a/openfpga_flow/VerilogNetlists/lb_tb.v +++ /dev/null @@ -1,199 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for logic blocks -// File Name : lb_tb.v -// Function : Configurable logic block -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module lb_tb; -// Parameters -parameter SIZE_IN = 40; //---- MUX input size -parameter SIZE_OUT = 10; //---- MUX input size -parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size -parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size -parameter prog_clk_period = 1; // [ns] half clock period -parameter op_clk_period = 1; // [ns] half clock period -parameter config_period = 2 * prog_clk_period; // [ns] One full clock period -parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period - -// Ports -wire [0:SIZE_IN-1] lb_in; -wire [0:SIZE_IN-1] lb_out; -wire lb_clk; -wire [0:SIZE_RESERV_BLWL-1] reserv_bl; -wire [0:SIZE_RESERV_BLWL-1] reserv_wl; -wire [0:SIZE_BLWL-1] bl; -wire [0:SIZE_BLWL-1] wl; -wire prog_EN; -wire prog_ENb; -wire zin; -wire nequalize; -wire read; -wire clk; -wire Reset; -wire Set; -// Clocks -wire prog_clock; -wire op_clock; - -// Registered port -reg [0:SIZE_IN-1] lb_in_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg; -reg [0:SIZE_BLWL-1] bl_reg; -reg [0:SIZE_BLWL-1] wl_reg; -reg prog_clock_reg; -reg op_clock_reg; - -// Config done signal; -reg config_done; -// Temp register for rotating shift -reg temp; - -// Unit under test -grid_1__1_ U0 ( -zin, -nequalize, -read, -clk, -Reset, -Set, -prog_ENb, -prog_EN, -// Top inputs -lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], -lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], -// Top outputs -lb_out[0], lb_out[4], lb_out[8], -// Right inputs -lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], -lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], -// Right outputs -lb_out[1], lb_out[5], lb_out[9], -// Bottom inputs -lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], -lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], -// Bottom outputs -lb_out[2], lb_out[6], -// Bottom inputs -lb_clk, -// left inputs -lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], -lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], -// left outputs -lb_out[3], lb_out[7], -reserv_bl, reserv_wl, -bl, wl -); - -// Task: assign BL and WL values -task prog_lb_blwl; - begin - @(posedge prog_clock); - // Rotate left shift - temp = reserv_bl_reg[SIZE_RESERV_BLWL-1]; - //bl_reg = bl_reg >> 1; - reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; - reserv_bl_reg[0] = temp; - end -endtask - -// Task: assign inputs -task op_lb_in; - begin - @(posedge op_clock); - temp = lb_in_reg[SIZE_IN-1]; - lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2]; - lb_in_reg[0] = temp; - end -endtask - -// Configuration done signal -initial -begin - config_done = 1'b0; -end -// Enabled during config_period, Disabled during op_period -always -begin - #config_period config_done = ~config_done; - #operating_period config_done = ~config_done; -end - -// Programming clocks -initial -begin - prog_clock_reg = 1'b0; -end -always -begin - #prog_clk_period prog_clock_reg = ~prog_clock_reg; -end - -// Operating clocks -initial -begin - op_clock_reg = 1'b0; -end -always -begin - #op_clk_period op_clock_reg = ~op_clock_reg; -end - -// Programming and Operating clocks -assign prog_clock = prog_clock_reg & (~config_done); -assign op_clock = op_clock_reg & config_done; - -// Programming Enable signals -assign prog_EN = prog_clock & (~config_done); -assign prog_ENb = ~prog_EN; - -// Programming phase: BL/WL -initial -begin - // Initialize BL/WL registers - reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; - reserv_bl_reg[0] = 1'b1; - reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; - // Reserved BL/WL - bl_reg = {SIZE_BLWL {1'b0}}; - wl_reg = {SIZE_BLWL {1'b1}}; - //wl_reg[SIZE_BLWL-1] = 1'b1; -end -always wait (~config_done) // Only invoked when config_done is 0 -begin - // Propagate input 1 to the output - // BL[0] = 1, WL[4] = 1 - prog_lb_blwl; -end - -// Operating Phase -initial -begin - lb_in_reg = {SIZE_IN {1'b0}}; - lb_in_reg[0] = 1'b1; // Last bit is 1 initially -end -always wait (config_done) // Only invoked when config_done is 1 -begin - /* Update inputs */ - op_lb_in; -end - -// Wire ports -assign lb_in = lb_in_reg; -assign reserv_bl = reserv_bl_reg; -assign reserv_wl = reserv_wl_reg; -assign bl = bl_reg; -assign wl = wl_reg; - -// Constant ports -assign zin = 1'b0; -assign nequalize = 1'b1; -assign read = 1'b0; -assign clk = op_clock; -assign Reset = ~config_done; -assign Set = 1'b0; - -endmodule From 019208ec0f195f609d0a85f65cdabe36274b0b98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 11:55:28 -0600 Subject: [PATCH 106/330] [Architecture] Reorganize the cell netlists and update architecture files accordingly --- .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_bank_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_resetb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_cc_use_setb_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_both_set_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_reset_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_resetb_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_set_openfpga.xml | 6 +++--- .../k4_N4_40nm_frame_use_setb_openfpga.xml | 6 +++--- .../k4_N4_40nm_powergate_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_N4_40nm_standalone_openfpga.xml | 6 +++--- .../k4_N4_no_local_routing_40nm_frame_openfpga.xml | 6 +++--- ..._N5_pattern_local_routing_40nm_frame_openfpga.xml | 6 +++--- .../openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml | 6 +++--- .../k4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 8 ++++---- ...frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml | 10 +++++----- ...N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml | 10 +++++----- ...er_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 12 ++++++------ openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml | 6 +++--- .../k6_N10_intermediate_buffer_40nm_openfpga.xml | 6 +++--- .../openfpga_arch/k6_frac_N10_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 8 ++++---- ...er_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml | 10 +++++----- ...frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 ++++++------ .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml | 8 ++++---- ...6_frac_N10_adder_register_chain_40nm_openfpga.xml | 8 ++++---- ...c_N10_adder_register_scan_chain_40nm_openfpga.xml | 8 ++++---- ...der_register_scan_chain_depop50_40nm_openfpga.xml | 8 ++++---- ...ister_scan_chain_depop50_spypad_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N10_behavioral_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_local_encoder_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_spyio_40nm_openfpga.xml | 6 +++--- .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N10_tree_mux_40nm_openfpga.xml | 6 +++--- .../openfpga_arch/k6_frac_N8_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_debuf_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_local_encoder_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml | 6 +++--- .../k6_frac_N8_stdcell_mux_40nm_openfpga.xml | 8 ++++---- .../k6_frac_N8_tree_mux_40nm_openfpga.xml | 6 +++--- .../spice}/adder.sp | 0 .../spice}/ff.sp | 0 .../spice}/gate.sp | 0 .../spice}/io.sp | 0 .../spice}/sram.sp | 0 .../spice_testbench}/ff_tb.sp | 0 .../verilog}/adder.v | 0 .../verilog}/aib.v | 0 .../verilog}/dff.v | 0 .../verilog}/dpram.v | 0 .../verilog}/dpram16k.v | 0 .../verilog}/dpram1k.v | 0 .../verilog}/frac_mem_32k.v | 0 .../verilog}/gpio.v | 0 .../verilog}/latch.v | 0 .../verilog}/lut6.v | 0 .../verilog}/mult_32x32.v | 0 .../verilog}/mult_36x36.v | 0 .../verilog}/mux2.v | 0 .../verilog}/sram.v | 0 .../verilog_testbench}/dpram_tb.v | 0 .../verilog_testbench}/ff_tb.v | 0 .../verilog_testbench}/mux_tb.v | 0 .../verilog_testbench}/sram_tb.v | 0 78 files changed, 186 insertions(+), 186 deletions(-) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/adder.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/ff.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/gate.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/io.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice}/sram.sp (100%) rename openfpga_flow/{SpiceNetlists => openfpga_cell_library/spice_testbench}/ff_tb.sp (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/adder.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/aib.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dff.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram16k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/dpram1k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/frac_mem_32k.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/gpio.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/latch.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/lut6.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mult_32x32.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mult_36x36.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/mux2.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog}/sram.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/dpram_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/ff_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/mux_tb.v (100%) rename openfpga_flow/{VerilogNetlists => openfpga_cell_library/verilog_testbench}/sram_tb.v (100%) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index e2ce76956..3acfc387c 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -155,7 +155,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index d8f97ba41..0fde86957 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 427889368..54b7dd8cc 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index d03b2d2be..22fcb70da 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml index fec761135..8ef6b9cf8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml index dc3c89739..477a013e2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index a36a863fd..5d368c49d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -146,7 +146,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index 762fc1af3..7cb74e9c2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -148,7 +148,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index c74d0aedb..56ce2b305 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml index 3e453fb3f..0afb065d8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml index 78461fadc..a99cb0cfa 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml index ee990043b..42dc751d2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -115,7 +115,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -147,7 +147,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index dced448a2..8dce74596 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 5d9aee9eb..bf7cad751 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index 92b7930c7..52e3a7091 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -155,7 +155,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml index ff3f2e1b0..c2d66f866 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -159,7 +159,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml index 7495f9c3b..9b54531dd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml index 0b7f14a25..93ba74c10 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml index f43436de5..634b95f7b 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml index cee0fbc79..8c0c8c692 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml index 7ba360992..2e4d554f8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index 0d03dc6d6..71629daf3 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -152,7 +152,7 @@ - + @@ -162,7 +162,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 3392eef23..3f1ebecad 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index cf0502130..0264a8862 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml index 6366425e0..3d4434c43 100644 --- a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index ceef842c0..1c5b5a300 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index beeb811e1..47db8c70a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index aed95c588..b800c806a 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index f5efbc285..0a5d0be89 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index af193a385..c41a0e40c 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + @@ -183,7 +183,7 @@ - + @@ -193,7 +193,7 @@ - + @@ -205,7 +205,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 9c8e66a87..cd348a131 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -146,7 +146,7 @@ - + @@ -156,7 +156,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index e0e8cd461..1e10c1f05 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -124,7 +124,7 @@ - + @@ -147,7 +147,7 @@ - + @@ -157,7 +157,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index 3afe5a693..a91b9eb01 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index adc3da01e..ad2bb7df9 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 1b2d8ffcb..70001d8e0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 2733b0317..f7c69d96a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index d900f0edb..49832b5f9 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + @@ -194,7 +194,7 @@ - + @@ -206,7 +206,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index b5439a151..d39983bbe 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index b22057acb..54e07fdae 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -175,7 +175,7 @@ - + @@ -184,7 +184,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 748f8ec48..299649ff0 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -170,7 +170,7 @@ - + @@ -180,7 +180,7 @@ - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 4335c3ae4..e0825a04e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -170,7 +170,7 @@ - + @@ -180,7 +180,7 @@ - + @@ -189,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 765bd94a1..30b76c135 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,7 +142,7 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + @@ -185,7 +185,7 @@ - + @@ -195,7 +195,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index a0d9be879..a5c49fc75 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index ef3bf9f21..b9aece61a 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index f9fcfe148..53e9ecc79 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index 588e88620..8dc34b2c5 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -86,7 +86,7 @@ If your standard cell provider does not offer the exact truth table, you can simply swap the inputs as shown in the example below --> - + @@ -131,7 +131,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -166,7 +166,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index da9767f10..1b001691d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 098e7ba2e..0abab4c71 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index 53dda3357..566968e41 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index f050bd8a7..a56d378b7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index ec3f99c4d..febd52470 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index cab4ef22b..48eacc3ba 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -139,7 +139,7 @@ - + @@ -164,7 +164,7 @@ - + @@ -174,7 +174,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index e367ff8bb..9e027bd22 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -86,7 +86,7 @@ If your standard cell provider does not offer the exact truth table, you can simply swap the inputs as shown in the example below --> - + @@ -131,7 +131,7 @@ - + @@ -156,7 +156,7 @@ - + @@ -166,7 +166,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index 0585bf591..486b8cd43 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -130,7 +130,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -165,7 +165,7 @@ - + diff --git a/openfpga_flow/SpiceNetlists/adder.sp b/openfpga_flow/openfpga_cell_library/spice/adder.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/adder.sp rename to openfpga_flow/openfpga_cell_library/spice/adder.sp diff --git a/openfpga_flow/SpiceNetlists/ff.sp b/openfpga_flow/openfpga_cell_library/spice/ff.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/ff.sp rename to openfpga_flow/openfpga_cell_library/spice/ff.sp diff --git a/openfpga_flow/SpiceNetlists/gate.sp b/openfpga_flow/openfpga_cell_library/spice/gate.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/gate.sp rename to openfpga_flow/openfpga_cell_library/spice/gate.sp diff --git a/openfpga_flow/SpiceNetlists/io.sp b/openfpga_flow/openfpga_cell_library/spice/io.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/io.sp rename to openfpga_flow/openfpga_cell_library/spice/io.sp diff --git a/openfpga_flow/SpiceNetlists/sram.sp b/openfpga_flow/openfpga_cell_library/spice/sram.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/sram.sp rename to openfpga_flow/openfpga_cell_library/spice/sram.sp diff --git a/openfpga_flow/SpiceNetlists/ff_tb.sp b/openfpga_flow/openfpga_cell_library/spice_testbench/ff_tb.sp similarity index 100% rename from openfpga_flow/SpiceNetlists/ff_tb.sp rename to openfpga_flow/openfpga_cell_library/spice_testbench/ff_tb.sp diff --git a/openfpga_flow/VerilogNetlists/adder.v b/openfpga_flow/openfpga_cell_library/verilog/adder.v similarity index 100% rename from openfpga_flow/VerilogNetlists/adder.v rename to openfpga_flow/openfpga_cell_library/verilog/adder.v diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/openfpga_cell_library/verilog/aib.v similarity index 100% rename from openfpga_flow/VerilogNetlists/aib.v rename to openfpga_flow/openfpga_cell_library/verilog/aib.v diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dff.v rename to openfpga_flow/openfpga_cell_library/verilog/dff.v diff --git a/openfpga_flow/VerilogNetlists/dpram.v b/openfpga_flow/openfpga_cell_library/verilog/dpram.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram.v diff --git a/openfpga_flow/VerilogNetlists/dpram16k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram16k.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram16k.v diff --git a/openfpga_flow/VerilogNetlists/dpram1k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram1k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram1k.v rename to openfpga_flow/openfpga_cell_library/verilog/dpram1k.v diff --git a/openfpga_flow/VerilogNetlists/frac_mem_32k.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v similarity index 100% rename from openfpga_flow/VerilogNetlists/frac_mem_32k.v rename to openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v similarity index 100% rename from openfpga_flow/VerilogNetlists/gpio.v rename to openfpga_flow/openfpga_cell_library/verilog/gpio.v diff --git a/openfpga_flow/VerilogNetlists/latch.v b/openfpga_flow/openfpga_cell_library/verilog/latch.v similarity index 100% rename from openfpga_flow/VerilogNetlists/latch.v rename to openfpga_flow/openfpga_cell_library/verilog/latch.v diff --git a/openfpga_flow/VerilogNetlists/lut6.v b/openfpga_flow/openfpga_cell_library/verilog/lut6.v similarity index 100% rename from openfpga_flow/VerilogNetlists/lut6.v rename to openfpga_flow/openfpga_cell_library/verilog/lut6.v diff --git a/openfpga_flow/VerilogNetlists/mult_32x32.v b/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mult_32x32.v rename to openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v diff --git a/openfpga_flow/VerilogNetlists/mult_36x36.v b/openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mult_36x36.v rename to openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v diff --git a/openfpga_flow/VerilogNetlists/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mux2.v rename to openfpga_flow/openfpga_cell_library/verilog/mux2.v diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/openfpga_cell_library/verilog/sram.v similarity index 100% rename from openfpga_flow/VerilogNetlists/sram.v rename to openfpga_flow/openfpga_cell_library/verilog/sram.v diff --git a/openfpga_flow/VerilogNetlists/dpram_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/dpram_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/dpram_tb.v diff --git a/openfpga_flow/VerilogNetlists/ff_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/ff_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/ff_tb.v diff --git a/openfpga_flow/VerilogNetlists/mux_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/mux_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v diff --git a/openfpga_flow/VerilogNetlists/sram_tb.v b/openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v similarity index 100% rename from openfpga_flow/VerilogNetlists/sram_tb.v rename to openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v From 6bea712db0989ddc0d541954e35e631aa389bf59 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 14:54:51 -0600 Subject: [PATCH 107/330] [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name --- .../src/fabric/build_essential_modules.cpp | 10 +++++- .../fpga_verilog/verilog_essential_gates.cpp | 36 +++++++++---------- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp index 19e1a10ea..3623ed259 100644 --- a/openfpga/src/fabric/build_essential_modules.cpp +++ b/openfpga/src/fabric/build_essential_modules.cpp @@ -256,7 +256,15 @@ void rename_primitive_module_port_names(ModuleManager& module_manager, /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) && (true == circuit_lib.model_spice_netlist(model).empty()) ) { - continue; + /* Exception circuit models as primitive cells + * - Inverter, buffer, pass-gate logic, logic gate + * which should be renamed even when auto-generated + */ + if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) + && (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(model)) + && (CIRCUIT_MODEL_GATE != circuit_lib.model_type(model)) ) { + continue; + } } /* Skip Routing channel wire models because they need a different name. Do it later */ if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index d33407071..ca3d38734 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -43,7 +43,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----")); /* Create a sensitive list */ - fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; + fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; fp << "\talways @("; /* Power-gate port first*/ @@ -52,10 +52,10 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, if (false == circuit_lib.port_is_config_enable(power_gate_port)) { continue; } - fp << circuit_lib.port_prefix(power_gate_port); + fp << circuit_lib.port_lib_name(power_gate_port); fp << ", "; } - fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ") begin" << std::endl; /* Dump the case of power-gated */ fp << "\t\tif ("; @@ -79,14 +79,14 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])"; + fp << circuit_lib.port_lib_name(power_gate_port) << "[" << power_gate_pin << "])"; port_cnt++; /* Update port counter*/ } } fp << ") begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = "; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -101,12 +101,12 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; fp << "\t\tend else begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl; fp << "\t\tend" << std::endl; fp << "\tend" << std::endl; - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; } /************************************************ @@ -124,7 +124,7 @@ void print_verilog_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : "; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -139,7 +139,7 @@ void print_verilog_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; } /************************************************ @@ -264,8 +264,8 @@ void print_verilog_passgate_module(const ModuleManager& module_manager, /* Dump logics: we propagate input to the output when the gate is '1' * the input is blocked from output when the gate is '0' */ - fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = "; - fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]); + fp << "\tassign " << circuit_lib.port_lib_name(output_ports[0]) << " = "; + fp << circuit_lib.port_lib_name(input_ports[1]) << " ? " << circuit_lib.port_lib_name(input_ports[0]); fp << " : 1'bz;" << std::endl; /* Print timing info */ @@ -311,7 +311,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, for (const auto& output_port : output_ports) { for (const auto& output_pin : circuit_lib.pins(output_port)) { - BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin); + BasicPort output_port_info(circuit_lib.port_lib_name(output_port), output_pin, output_pin); fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info); fp << " = "; @@ -323,7 +323,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, fp << " " << gate_verilog_operator << " "; } - BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin); + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), input_pin, input_pin); fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); /* Increment the counter for port */ @@ -395,10 +395,10 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * the third input is the select port */ fp << "\tassign "; - BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0); - BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0); - BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0); - BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0); + BasicPort out_port_info(circuit_lib.port_lib_name(output_ports[0]), 0, 0); + BasicPort sel_port_info(circuit_lib.port_lib_name(input_ports[2]), 0, 0); + BasicPort in0_port_info(circuit_lib.port_lib_name(input_ports[0]), 0, 0); + BasicPort in1_port_info(circuit_lib.port_lib_name(input_ports[1]), 0, 0); fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info); fp << " = "; From 1b4e4491799d4eed93bfa5e18c15d69d2b725e47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:05:20 -0600 Subject: [PATCH 108/330] [OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol --- .../fpga_verilog/verilog_top_testbench.cpp | 132 ++++++++++++------ .../src/fpga_verilog/verilog_writer_utils.cpp | 51 +++++++ .../src/fpga_verilog/verilog_writer_utils.h | 6 + 3 files changed, 148 insertions(+), 41 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index c4250bdcc..a63ef38ef 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -178,21 +178,34 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, wl_addr_port) << ";" << std::endl; /* Print the data-input port for the frame-based decoder here */ - print_verilog_comment(fp, std::string("---- Data input port for frame-based decoder -----")); + print_verilog_comment(fp, std::string("---- Data input port for memory decoders -----")); ModulePortId din_port_id = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME)); BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED configuration done signal to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); + /* Generate enable signal waveform here: + * which is a 90 degree phase shift than the programming clock + */ + print_verilog_comment(fp, std::string("---- Wire enable port of memory decoders -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); + fp << generate_verilog_port(VERILOG_PORT_REG, en_register_port) << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, en_port); + fp << "= "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, en_register_port); + fp << " & "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << ";" << std::endl; } @@ -201,8 +214,6 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, - const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { /* Validate the file stream */ @@ -223,33 +234,28 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED configuration done signal to the enable signal !!! */ + /* Generate enable signal waveform here: + * which is a 90 degree phase shift than the programming clock + */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoders -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); - /* Find the circuit model of configurable memory - * Spot its BL port and generate stimuli based on BL port's attribute: - * - If the BL port is triggered by edge, use the inverted programming clock signal - * - If the BL port is a regular port, use the inverted configuration done signal - */ - const CircuitModelId& mem_model = config_protocol.memory_model(); - VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model)); - std::vector mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL); - VTR_ASSERT(1 == mem_model_bl_ports.size()); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) { - VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----")); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); - } else { - BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, config_done_port, true); - } + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_REG, en_register_port) << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, en_port); + fp << "= "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, en_register_port); + fp << " & "; + fp << "~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << ";" << std::endl; } /******************************************************************** @@ -258,7 +264,6 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, static void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { switch(config_protocol.type()) { @@ -272,7 +277,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib, + print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module); break; default: @@ -525,7 +530,6 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, const ConfigProtocol& config_protocol, - const CircuitLibrary& circuit_lib, const std::string& circuit_name){ /* Validate the file stream */ valid_file_stream(fp); @@ -599,7 +603,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib, + print_verilog_top_testbench_config_protocol_port(fp, config_protocol, module_manager, top_module); /* Create a clock port if the benchmark have one but not in the default name! @@ -816,9 +820,7 @@ void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& f /* Validate the file stream */ valid_file_stream(fp); - ModulePortId en_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME)); @@ -851,7 +853,7 @@ void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& f fp << generate_verilog_port(VERILOG_PORT_INPUT, wl_addr_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; fp << "\tbegin" << std::endl; - fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl; + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; fp << "\t\t\t"; fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port); @@ -898,9 +900,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& /* Validate the file stream */ valid_file_stream(fp); - ModulePortId en_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); ModulePortId addr_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ADDRESS_PORT_NAME)); @@ -926,7 +926,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; fp << "\tbegin" << std::endl; - fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl; + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; fp << "\t\t\t"; fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port); @@ -1113,6 +1113,49 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Print input stimuli for configuration protocol + * include: + * - memory bank + * 1. the enable signal + * - frame-based + * 1. the enable signal + *******************************************************************/ +static +void print_verilog_top_testbench_configuration_protocol_stimulus(std::fstream& fp, + const e_config_protocol_type& config_protocol_type, + const ModuleManager& module_manager, + const ModuleId& top_module, + const float& prog_clock_period, + const float& timescale) { + /* Validate the file stream */ + valid_file_stream(fp); + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: + break; + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + ModulePortId en_port_id = module_manager.find_module_port(top_module, + std::string(DECODER_ENABLE_PORT_NAME)); + BasicPort en_port = module_manager.module_port(top_module, en_port_id); + BasicPort en_register_port(std::string(en_port.get_name() + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1); + print_verilog_comment(fp, std::string("---- Generate enable signal waveform -----")); + print_verilog_shifted_clock_stimuli(fp, en_register_port, + 0.25 * prog_clock_period / timescale, + 0.5 * prog_clock_period / timescale, 0); + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid SRAM organization type!\n"); + exit(1); + } +} + /******************************************************************** * Print stimulus for a FPGA fabric with a flatten memory (standalone) configuration protocol * We will load the bitstream in the second clock cycle, right after the first reset cycle @@ -1711,7 +1754,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, - config_protocol, circuit_lib, + config_protocol, circuit_name); /* Find the clock period */ @@ -1731,6 +1774,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, op_clock_period, VERILOG_SIM_TIMESCALE); + /* Generate stimuli for programming interface */ + print_verilog_top_testbench_configuration_protocol_stimulus(fp, + config_protocol.type(), + module_manager, top_module, + prog_clock_period, + VERILOG_SIM_TIMESCALE); + /* Identify the stimulus for global reset/set for programming purpose: * - If only reset port is seen we turn on Reset * - If only set port is seen we turn on Reset diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index 2817ccbaf..bc41f1cab 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -1294,6 +1294,57 @@ void print_verilog_pulse_stimuli(std::fstream& fp, fp << std::endl; } + +/******************************************************************** + * Print stimuli for a clock pulse generation + * This function supports the delay at the beginning of the waveform + * + * |<-- Initial delay -->|<--- pulse width --->| + * +------ flip_value + * | + * initial_value --------------------------------------------+ + * + *******************************************************************/ +void print_verilog_shifted_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const float& initial_delay, + const float& pulse_width, + const size_t& initial_value) { + /* Validate the file stream */ + VTR_ASSERT(true == valid_file_stream(fp)); + + /* Config_done signal: indicate when configuration is finished */ + fp << "initial" << std::endl; + + write_tab_to_file(fp, 1); + fp << "begin" << std::endl; + + write_tab_to_file(fp, 1); + std::vector initial_values(port.get_width(), initial_value); + + write_tab_to_file(fp, 1); + fp << generate_verilog_port_constant_values(port, initial_values); + fp << ";" << std::endl; + + write_tab_to_file(fp, 2); + fp << "#" << std::setprecision(10) << initial_delay; + fp << ";" << std::endl; + + write_tab_to_file(fp, 2); + fp << "forever "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << " = "; + fp << "#" << std::setprecision(10) << pulse_width; + fp << " ~" << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << ";" << std::endl; + + write_tab_to_file(fp, 1); + fp << "end" << std::endl; + + /* Print an empty line as splitter */ + fp << std::endl; +} + /******************************************************************** * Print stimuli for a pulse generation * This function supports multiple signal switching under different pulse width diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 21c12509b..fd1c9b1a5 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -161,6 +161,12 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, const size_t& num_conf_bits, const BasicPort& fm_config_bus); +void print_verilog_shifted_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const float& initial_delay, + const float& pulse_width, + const size_t& initial_value); + void print_verilog_pulse_stimuli(std::fstream& fp, const BasicPort& port, const size_t& initial_value, From dcbd6a06140701a3ad40052db746f6de87e6754f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:08:12 -0600 Subject: [PATCH 109/330] [Architecture] Add lib name to TGATE to test compatibility --- .../openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index 1c5b5a300..b33049ae7 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -84,10 +84,10 @@ - - - - + + + + 10e-12 5e-12 5e-12 From ffd926d68679b782561dfc867dc5886b9ed702b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Sep 2020 21:30:59 -0600 Subject: [PATCH 110/330] [Architecture] Update external bitstream --- .../and2_k4_N4_tileable_40nm_bitstream.xml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index 07a874f86..28d1265f6 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Thu Sep 24 20:16:32 2020 + - Date: Fri Sep 25 21:30:07 2020 --> @@ -1286,20 +1286,20 @@ - + - + - + - - + + - + - + - + From 154f23b108a8e646db07d79a27d04a679eea0054 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 11:54:06 -0600 Subject: [PATCH 111/330] [OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches --- .../fpga_verilog/verilog_top_testbench.cpp | 48 ++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index a63ef38ef..2d957b6b6 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -641,8 +641,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Instantiate an integer to count the number of error and * determine if the simulation succeed or failed */ - print_verilog_comment(fp, std::string("----- Error counter -----")); - fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl; + print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----")); + fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl; } /******************************************************************** @@ -1675,6 +1675,44 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, } } +/******************************************************************** + * Add auto-check codes for the full testbench + * in particular for the configuration phase: + * - Check that the configuration done signal is raised, indicating + * that the configuration phase is finished + *******************************************************************/ +static +void print_verilog_top_testbench_check(std::fstream& fp, + const std::string& autochecked_preprocessing_flag, + const std::string& config_done_port_name, + const std::string& error_counter_name) { + + /* Validate the file stream */ + valid_file_stream(fp); + + /* Add output autocheck conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); + + print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------")); + + BasicPort config_done_port(config_done_port_name, 1); + + write_tab_to_file(fp, 1); + fp << "always@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ") begin" << std::endl; + + write_tab_to_file(fp, 2); + fp << error_counter_name << " = " << error_counter_name << " - 1;" << std::endl; + + write_tab_to_file(fp, 1); + fp << "end" << std::endl; + + /* Condition ends */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + /******************************************************************** * The top-level function to generate a testbench, in order to verify: * 1. Configuration phase of the FPGA fabric, where the bitstream is @@ -1866,6 +1904,12 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, clock_port_names, std::string(TOP_TB_OP_CLOCK_PORT_NAME)); + /* Add autocheck for configuration phase */ + print_verilog_top_testbench_check(fp, + std::string(AUTOCHECKED_SIMULATION_FLAG), + std::string(TOP_TB_CONFIG_DONE_PORT_NAME), + std::string(TOP_TESTBENCH_ERROR_COUNTER)); + /* Find simulation time */ float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE, num_config_clock_cycles, From 51d96244c616d0338894ea95babf307edc17dae2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 14:30:57 -0600 Subject: [PATCH 112/330] [OpenFPGA Tool] Remove deprecated XML syntax --- .../libarchopenfpga/src/circuit_library.cpp | 15 ------------ .../libarchopenfpga/src/circuit_library.h | 23 ++++++++----------- .../src/read_xml_circuit_library.cpp | 3 --- .../src/write_xml_circuit_library.cpp | 4 ---- 4 files changed, 9 insertions(+), 36 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index d8069f903..55dfe8130 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,11 +942,6 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } -bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_edge_triggered_[circuit_port_id]; -} /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { @@ -1380,7 +1375,6 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); - port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); @@ -1500,15 +1494,6 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } -/* Set the is_edge_triggered for a port of a circuit model */ -void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; - return; -} - /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index f4b742a27..bd082f738 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,16 +91,15 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop - * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 16. port_inv_model_names_: the name of inverter circuit model linked to the port - * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 15. port_inv_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -285,7 +284,6 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; - bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -366,8 +364,6 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -554,7 +550,6 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; - vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 4136b0463..36e837814 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,9 +564,6 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Identify if the port is to triggered by edges, by default it is NOT */ - circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 9165725e2..b141b0fe2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,10 +207,6 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } - if (true == circuit_lib.port_is_edge_triggered(port)) { - write_xml_attribute(fp, "is_edge_triggered", "true"); - } - /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str()); From 94a1324f0527276546c3b2571b1a1b7700a473f7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Sep 2020 14:31:57 -0600 Subject: [PATCH 113/330] [Documentation] Remove deprecated XML syntax --- docs/source/manual/arch_lang/circuit_library.rst | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 9e8466c09..59e5f055f 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,8 +143,7 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -191,8 +190,6 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. - - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. - .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details. From 94047037c570b6a432fea8f363a5147df9bc918d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 14:33:14 -0600 Subject: [PATCH 114/330] [OpenFPGA Tool] Streamline codes in openfpga arch parser --- .../src/read_xml_circuit_library.cpp | 166 ++++-------------- .../src/read_xml_config_protocol.cpp | 19 +- .../src/read_xml_simulation_setting.cpp | 10 +- .../src/read_xml_technology_library.cpp | 20 +-- 4 files changed, 53 insertions(+), 162 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 36e837814..86b1de94e 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -26,52 +26,10 @@ *******************************************************************/ static e_circuit_model_type string_to_circuit_model_type(const std::string& type_string) { - if (std::string("chan_wire") == type_string) { - return CIRCUIT_MODEL_CHAN_WIRE; - } - - if (std::string("wire") == type_string) { - return CIRCUIT_MODEL_WIRE; - } - - if (std::string("mux") == type_string) { - return CIRCUIT_MODEL_MUX; - } - - if (std::string("lut") == type_string) { - return CIRCUIT_MODEL_LUT; - } - - if (std::string("ff") == type_string) { - return CIRCUIT_MODEL_FF; - } - - if (std::string("sram") == type_string) { - return CIRCUIT_MODEL_SRAM; - } - - if (std::string("hard_logic") == type_string) { - return CIRCUIT_MODEL_HARDLOGIC; - } - - if (std::string("ccff") == type_string) { - return CIRCUIT_MODEL_CCFF; - } - - if (std::string("iopad") == type_string) { - return CIRCUIT_MODEL_IOPAD; - } - - if (std::string("inv_buf") == type_string) { - return CIRCUIT_MODEL_INVBUF; - } - - if (std::string("pass_gate") == type_string) { - return CIRCUIT_MODEL_PASSGATE; - } - - if (std::string("gate") == type_string) { - return CIRCUIT_MODEL_GATE; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } /* Reach here, we have an invalid value, error out */ @@ -83,12 +41,10 @@ e_circuit_model_type string_to_circuit_model_type(const std::string& type_string *******************************************************************/ static e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_string) { - if (std::string("cmos") == type_string) { - return CIRCUIT_MODEL_DESIGN_CMOS; - } - - if (std::string("rram") == type_string) { - return CIRCUIT_MODEL_DESIGN_RRAM; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES; @@ -99,12 +55,10 @@ e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_s *******************************************************************/ static e_circuit_model_buffer_type string_to_buffer_type(const std::string& type_string) { - if (std::string("inverter") == type_string) { - return CIRCUIT_MODEL_BUF_INV; - } - - if (std::string("buffer") == type_string) { - return CIRCUIT_MODEL_BUF_BUF; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_BUF_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_BUFFER_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_BUF_TYPES; @@ -115,12 +69,10 @@ e_circuit_model_buffer_type string_to_buffer_type(const std::string& type_string *******************************************************************/ static e_circuit_model_pass_gate_logic_type string_to_passgate_type(const std::string& type_string) { - if (std::string("transmission_gate") == type_string) { - return CIRCUIT_MODEL_PASS_GATE_TRANSMISSION; - } - - if (std::string("pass_transistor") == type_string) { - return CIRCUIT_MODEL_PASS_GATE_TRANSISTOR; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_PASS_GATE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_PASSGATE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_PASS_GATE_TYPES; @@ -131,16 +83,10 @@ e_circuit_model_pass_gate_logic_type string_to_passgate_type(const std::string& *******************************************************************/ static e_circuit_model_structure string_to_mux_structure_type(const std::string& type_string) { - if (std::string("tree") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_TREE; - } - - if (std::string("one_level") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_ONELEVEL; - } - - if (std::string("multi_level") == type_string) { - return CIRCUIT_MODEL_STRUCTURE_MULTILEVEL; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_STRUCTURE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_STRUCTURE_TYPES; @@ -151,16 +97,10 @@ e_circuit_model_structure string_to_mux_structure_type(const std::string& type_s *******************************************************************/ static e_circuit_model_gate_type string_to_gate_type(const std::string& type_string) { - if (std::string("AND") == type_string) { - return CIRCUIT_MODEL_GATE_AND; - } - - if (std::string("OR") == type_string) { - return CIRCUIT_MODEL_GATE_OR; - } - - if (std::string("MUX2") == type_string) { - return CIRCUIT_MODEL_GATE_MUX2; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_GATE_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_GATE_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_GATE_TYPES; @@ -171,40 +111,10 @@ e_circuit_model_gate_type string_to_gate_type(const std::string& type_string) { *******************************************************************/ static e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& type_string) { - if (std::string("input") == type_string) { - return CIRCUIT_MODEL_PORT_INPUT; - } - - if (std::string("output") == type_string) { - return CIRCUIT_MODEL_PORT_OUTPUT; - } - - if (std::string("clock") == type_string) { - return CIRCUIT_MODEL_PORT_CLOCK; - } - - if (std::string("sram") == type_string) { - return CIRCUIT_MODEL_PORT_SRAM; - } - - if (std::string("bl") == type_string) { - return CIRCUIT_MODEL_PORT_BL; - } - - if (std::string("wl") == type_string) { - return CIRCUIT_MODEL_PORT_WL; - } - - if (std::string("blb") == type_string) { - return CIRCUIT_MODEL_PORT_BLB; - } - - if (std::string("wlb") == type_string) { - return CIRCUIT_MODEL_PORT_WLB; - } - - if (std::string("inout") == type_string) { - return CIRCUIT_MODEL_PORT_INOUT; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_PORT_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_PORT_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_PORT_TYPES; @@ -215,12 +125,10 @@ e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& t *******************************************************************/ static e_wire_model_type string_to_wire_model_type(const std::string& type_string) { - if (std::string("pi") == type_string) { - return WIRE_MODEL_PI; - } - - if (std::string("t") == type_string) { - return WIRE_MODEL_T; + for (size_t itype = 0; itype < NUM_WIRE_MODEL_TYPES; ++itype) { + if (std::string(WIRE_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_WIRE_MODEL_TYPES; @@ -231,12 +139,10 @@ e_wire_model_type string_to_wire_model_type(const std::string& type_string) { *******************************************************************/ static e_circuit_model_delay_type string_to_circuit_model_delay_type(const std::string& type_string) { - if (std::string("rise") == type_string) { - return CIRCUIT_MODEL_DELAY_RISE; - } - - if (std::string("fall") == type_string) { - return CIRCUIT_MODEL_DELAY_FALL; + for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_DELAY_TYPES; ++itype) { + if (std::string(CIRCUIT_MODEL_DELAY_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CIRCUIT_MODEL_DELAY_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp index 2daedbd39..04833d33a 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -23,20 +23,11 @@ *******************************************************************/ static e_config_protocol_type string_to_config_protocol_type(const std::string& type_string) { - if (std::string("standalone") == type_string) { - return CONFIG_MEM_STANDALONE; - } - - if (std::string("scan_chain") == type_string) { - return CONFIG_MEM_SCAN_CHAIN; - } - - if (std::string("memory_bank") == type_string) { - return CONFIG_MEM_MEMORY_BANK; - } - - if (std::string("frame_based") == type_string) { - return CONFIG_MEM_FRAME_BASED; + + for (size_t itype = 0; itype < NUM_CONFIG_PROTOCOL_TYPES; ++itype) { + if (std::string(CONFIG_PROTOCOL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_CONFIG_PROTOCOL_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp index 6007a14bf..cf8bc11b9 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp @@ -23,12 +23,10 @@ *******************************************************************/ static e_sim_accuracy_type string_to_sim_accuracy_type(const std::string& type_string) { - if (std::string("frac") == type_string) { - return SIM_ACCURACY_FRAC; - } - - if (std::string("abs") == type_string) { - return SIM_ACCURACY_ABS; + for (size_t itype = 0; itype < NUM_SIM_ACCURACY_TYPES; ++itype) { + if (std::string(SIM_ACCURACY_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_SIM_ACCURACY_TYPES; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp index e2871a638..9c5c2b132 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_technology_library.cpp @@ -23,12 +23,10 @@ *******************************************************************/ static e_tech_lib_model_type string_to_device_model_type(const std::string& type_string) { - if (std::string("transistor") == type_string) { - return TECH_LIB_MODEL_TRANSISTOR; - } - - if (std::string("rram") == type_string) { - return TECH_LIB_MODEL_RRAM; + for (size_t itype = 0; itype < NUM_TECH_LIB_MODEL_TYPES; ++itype) { + if (std::string(TECH_LIB_MODEL_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_TECH_LIB_MODEL_TYPES; @@ -39,12 +37,10 @@ e_tech_lib_model_type string_to_device_model_type(const std::string& type_string *******************************************************************/ static e_tech_lib_type string_to_tech_lib_type(const std::string& type_string) { - if (std::string("industry") == type_string) { - return TECH_LIB_INDUSTRY; - } - - if (std::string("academia") == type_string) { - return TECH_LIB_ACADEMIA; + for (size_t itype = 0; itype < NUM_TECH_LIB_TYPES; ++itype) { + if (std::string(TECH_LIB_TYPE_STRING[itype]) == type_string) { + return static_cast(itype); + } } return NUM_TECH_LIB_TYPES; From bbdea4a46b7aadd8a6f0fc45abdd39d1cc6d3057 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 19:23:13 -0600 Subject: [PATCH 115/330] [Regression Test] Remove out-of-update sub modules --- .gitmodules | 3 --- 1 file changed, 3 deletions(-) delete mode 100644 .gitmodules diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index bb17c5f21..000000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "OpenSTA"] - path = OpenSTA - url = https://github.com/abk-openroad/OpenSTA From 48b2bff0d909e2c6d0740d2a5386123eb238349f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 20:08:11 -0600 Subject: [PATCH 116/330] [OpenFPGA Tool] Update fabric key data structure to support regions --- .../libfabrickey/key_examples/key_example.xml | 12 +-- libopenfpga/libfabrickey/src/fabric_key.cpp | 80 ++++++++++++++++++- libopenfpga/libfabrickey/src/fabric_key.h | 58 +++++++++++++- libopenfpga/libfabrickey/src/fabric_key_fwd.h | 2 + 4 files changed, 142 insertions(+), 10 deletions(-) diff --git a/libopenfpga/libfabrickey/key_examples/key_example.xml b/libopenfpga/libfabrickey/key_examples/key_example.xml index 49140b6e0..b9b0aa814 100644 --- a/libopenfpga/libfabrickey/key_examples/key_example.xml +++ b/libopenfpga/libfabrickey/key_examples/key_example.xml @@ -1,7 +1,9 @@ - - - - - + + + + + + + diff --git a/libopenfpga/libfabrickey/src/fabric_key.cpp b/libopenfpga/libfabrickey/src/fabric_key.cpp index b4bf5efac..dfe445c75 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/fabric_key.cpp @@ -1,4 +1,7 @@ +#include + #include "vtr_assert.h" +#include "vtr_log.h" #include "fabric_key.h" @@ -20,24 +23,31 @@ FabricKey::fabric_key_range FabricKey::keys() const { return vtr::make_range(key_ids_.begin(), key_ids_.end()); } +FabricKey::fabric_region_range FabricKey::regions() const { + return vtr::make_range(region_ids_.begin(), region_ids_.end()); +} + /************************************************************************ * Public Accessors : Basic data query ***********************************************************************/ -/* Access the name of a key */ +std::vector FabricKey::region_keys(const FabricRegionId& region_id) const { + /* validate the region_id */ + VTR_ASSERT(valid_region_id(region_id)); + return region_key_ids_[region_id]; +} + std::string FabricKey::key_name(const FabricKeyId& key_id) const { /* validate the key_id */ VTR_ASSERT(valid_key_id(key_id)); return key_names_[key_id]; } -/* Access the value of a key */ size_t FabricKey::key_value(const FabricKeyId& key_id) const { /* validate the key_id */ VTR_ASSERT(valid_key_id(key_id)); return key_values_[key_id]; } -/* Access the alias of a key */ std::string FabricKey::key_alias(const FabricKeyId& key_id) const { /* validate the key_id */ VTR_ASSERT(valid_key_id(key_id)); @@ -51,20 +61,78 @@ bool FabricKey::empty() const { /************************************************************************ * Public Mutators ***********************************************************************/ + +void FabricKey::reserve_regions(const size_t& num_regions) { + region_ids_.reserve(num_regions); + region_key_ids_.reserve(num_regions); +} + +FabricRegionId FabricKey::create_region() { + /* Create a new id */ + FabricRegionId region = FabricRegionId(region_ids_.size()); + region_ids_.push_back(region); + region_key_ids_.emplace_back(); + + return region; +} + +void FabricKey::reserve_region_keys(const FabricRegionId& region_id, + const size_t& num_keys) { + /* validate the region_id */ + VTR_ASSERT(valid_region_id(region_id)); + + region_key_ids_[region_id].reserve(num_keys); +} + +void FabricKey::add_key_to_region(const FabricRegionId& region_id, + const FabricKeyId& key_id) { + /* validate the key_id */ + VTR_ASSERT(valid_key_id(key_id)); + /* validate the region_id */ + VTR_ASSERT(valid_region_id(region_id)); + + /* Check if the key is already in the region */ + if (region_key_ids_[region_id].end() != std::find(region_key_ids_[region_id].begin(), + region_key_ids_[region_id].end(), + key_id)) { + VTR_LOG_WARN("Try to add a key '%s' which is already in the region '%lu'!\n", + key_name(key_id).c_str(), + size_t(region_id)); + VTR_ASSERT(region_id == key_regions_[key_id]); + return; /* Nothing to do but leave a warning! */ + } + + /* Register the key in the region */ + region_key_ids_[region_id].push_back(key_id); + + /* If the key is already in another region, we will error out */ + if ( (true == valid_region_id(key_regions_[key_id])) + && (region_id != key_regions_[key_id])) { + VTR_LOG_ERROR("Try to add a key '%s' to region '%lu' but it is already in another region '%lu'!\n", + key_name(key_id).c_str(), + size_t(key_regions_[key_id]), + size_t(region_id)); + exit(1); + } + + key_regions_[key_id] = region_id; +} + void FabricKey::reserve_keys(const size_t& num_keys) { key_ids_.reserve(num_keys); key_names_.reserve(num_keys); key_values_.reserve(num_keys); + key_regions_.reserve(num_keys); key_alias_.reserve(num_keys); } -/* Create a new key and add it to the library, return an id */ FabricKeyId FabricKey::create_key() { /* Create a new id */ FabricKeyId key = FabricKeyId(key_ids_.size()); key_ids_.push_back(key); key_names_.emplace_back(); key_values_.emplace_back(); + key_regions_.emplace_back(FabricRegionId::INVALID()); key_alias_.emplace_back(); return key; @@ -98,6 +166,10 @@ void FabricKey::set_key_alias(const FabricKeyId& key_id, * Internal invalidators/validators ***********************************************************************/ /* Validators */ +bool FabricKey::valid_region_id(const FabricRegionId& region_id) const { + return ( size_t(region_id) < region_ids_.size() ) && ( region_id == region_ids_[region_id] ); +} + bool FabricKey::valid_key_id(const FabricKeyId& key_id) const { return ( size_t(key_id) < key_ids_.size() ) && ( key_id == key_ids_[key_id] ); } diff --git a/libopenfpga/libfabrickey/src/fabric_key.h b/libopenfpga/libfabrickey/src/fabric_key.h index 4ca678722..0ca1d252d 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.h +++ b/libopenfpga/libfabrickey/src/fabric_key.h @@ -15,41 +15,94 @@ /******************************************************************** * A data structure to describe a secure key for fabric organization + * A fabric may consist of multiple regions + * Each region contains a number of keys + * + * Note that: + * - each key can only be defined in one unique region * * Typical usage: * -------------- * // Create an empty fabric key * FabricKey fabric_key; + * // Create a region + * FabricRegionId region = fabric_key.create_region(); * // Add a key with name and value - * FabricKeyId key = fabic_key.create_key(key_name, key_value); + * FabricKeyId key = fabric_key.create_key(key_name, key_value); + * // Affilate a key to a region + * fabric_key.add_key_to_region(region, key); * *******************************************************************/ class FabricKey { public: /* Types */ typedef vtr::vector::const_iterator fabric_key_iterator; + typedef vtr::vector::const_iterator fabric_region_iterator; /* Create range */ + typedef vtr::Range fabric_region_range; typedef vtr::Range fabric_key_range; public: /* Constructors */ FabricKey(); public: /* Accessors: aggregates */ fabric_key_range keys() const; + fabric_region_range regions() const; public: /* Public Accessors: Basic data query */ + /* Access all the keys of a region */ + std::vector region_keys(const FabricRegionId& region_id) const; + + /* Access the name of a key */ std::string key_name(const FabricKeyId& key_id) const; + + /* Access the value of a key */ size_t key_value(const FabricKeyId& key_id) const; + + /* Access the alias of a key */ std::string key_alias(const FabricKeyId& key_id) const; + + /* Check if there are any keys */ bool empty() const; + public: /* Public Mutators: model-related */ + + /* Reserve a number of regions to be memory efficent */ + void reserve_regions(const size_t& num_regions); + + /* Create a new region and add it to the library, return an id */ + FabricRegionId create_region(); + + /* Reserve the memory space for keys under a region, to be memory efficient */ + void reserve_region_keys(const FabricRegionId& region_id, + const size_t& num_keys); + + /* Add a key to a region */ + void add_key_to_region(const FabricRegionId& region_id, + const FabricKeyId& key_id); + + /* Reserve a number of keys to be memory efficent */ void reserve_keys(const size_t& num_keys); + + /* Create a new key and add it to the library, return an id */ FabricKeyId create_key(); + + /* Configure attributes of a key */ void set_key_name(const FabricKeyId& key_id, const std::string& name); + void set_key_value(const FabricKeyId& key_id, const size_t& value); + void set_key_alias(const FabricKeyId& key_id, const std::string& alias); + public: /* Public invalidators/validators */ + bool valid_region_id(const FabricRegionId& region_id) const; bool valid_key_id(const FabricKeyId& key_id) const; private: /* Internal data */ + /* Unique ids for each region */ + vtr::vector region_ids_; + + /* Key ids for each region */ + vtr::vector> region_key_ids_; + /* Unique ids for each key */ vtr::vector key_ids_; @@ -59,6 +112,9 @@ class FabricKey { /* Values for each key */ vtr::vector key_values_; + /* Region for each key */ + vtr::vector key_regions_; + /* Optional alias for each key, with which a key can also be represented */ vtr::vector key_alias_; }; diff --git a/libopenfpga/libfabrickey/src/fabric_key_fwd.h b/libopenfpga/libfabrickey/src/fabric_key_fwd.h index 523eaeab8..249093fd2 100644 --- a/libopenfpga/libfabrickey/src/fabric_key_fwd.h +++ b/libopenfpga/libfabrickey/src/fabric_key_fwd.h @@ -12,8 +12,10 @@ #include "vtr_strong_id.h" +struct fabric_region_id_tag; struct fabric_key_id_tag; +typedef vtr::StrongId FabricRegionId; typedef vtr::StrongId FabricKeyId; /* Short declaration of class */ From e09e5fa6c6f4f36ea196ac208eef536ab834f18a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 20:40:37 -0600 Subject: [PATCH 117/330] [Architecture] Update fabric key for region syntax --- .../fabric_keys/k4_N4_2x2_sample_key.xml | 68 ++++++++++--------- 1 file changed, 35 insertions(+), 33 deletions(-) diff --git a/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml index 81716fb00..2ce5bfa52 100644 --- a/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml +++ b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml @@ -1,35 +1,37 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 491433fae2291e57592c4aedc041dec512763e8b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 20:41:01 -0600 Subject: [PATCH 118/330] [OpenFPGA Tool] Update XML parser for fabric regions --- .../libfabrickey/src/read_xml_fabric_key.cpp | 74 ++++++++++++++++--- .../libfabrickey/src/write_xml_fabric_key.cpp | 24 ++++-- 2 files changed, 82 insertions(+), 16 deletions(-) diff --git a/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp index 7bc42b54e..f509ddc79 100644 --- a/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp @@ -23,17 +23,19 @@ * Parse XML codes of a to an object of FabricKey *******************************************************************/ static -void read_xml_component_key(pugi::xml_node& xml_component_key, - const pugiutil::loc_data& loc_data, - FabricKey& fabric_key) { +void read_xml_region_key(pugi::xml_node& xml_component_key, + const pugiutil::loc_data& loc_data, + FabricKey& fabric_key, + const FabricRegionId& fabric_region) { /* Find the id of component key */ const size_t& id = get_attribute(xml_component_key, "id", loc_data).as_int(); if (false == fabric_key.valid_key_id(FabricKeyId(id))) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_component_key), - "Invalid 'id' attribute '%d'\n", - id); + "Invalid 'id' attribute '%d' (in total %lu keys)!\n", + id, + fabric_key.keys().size()); } VTR_ASSERT_SAFE(true == fabric_key.valid_key_id(FabricKeyId(id))); @@ -57,6 +59,41 @@ void read_xml_component_key(pugi::xml_node& xml_component_key, fabric_key.set_key_name(FabricKeyId(id), name); fabric_key.set_key_value(FabricKeyId(id), value); + fabric_key.add_key_to_region(fabric_region, FabricKeyId(id)); +} + +/******************************************************************** + * Parse XML codes of a to an object of FabricKey + *******************************************************************/ +static +void read_xml_fabric_region(pugi::xml_node& xml_region, + const pugiutil::loc_data& loc_data, + FabricKey& fabric_key) { + /* Find the unique id for the region */ + const FabricRegionId& region_id = FabricRegionId(get_attribute(xml_region, "id", loc_data).as_int()); + if (false == fabric_key.valid_region_id(region_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_region), + "Invalid region id '%lu' (in total %lu regions)!\n", + size_t(region_id), + fabric_key.regions().size()); + } + VTR_ASSERT_SAFE(true == fabric_key.valid_region_id(region_id)); + + /* Reserve memory space for the keys in the region */ + size_t num_keys = std::distance(xml_region.children().begin(), xml_region.children().end()); + fabric_key.reserve_region_keys(region_id, num_keys); + + for (pugi::xml_node xml_key : xml_region.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_key.name() != std::string("key")) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_region), + "Unexpected child '%s' in region '%lu', Region XML node can only contain keys!\n", + xml_key.name(), + size_t(region_id)); + } + /* Parse the key for this region */ + read_xml_region_key(xml_key, loc_data, fabric_key, region_id); + } } /******************************************************************** @@ -77,7 +114,24 @@ FabricKey read_xml_fabric_key(const char* key_fname) { pugi::xml_node xml_root = get_single_child(doc, "fabric_key", loc_data); - size_t num_keys = std::distance(xml_root.children().begin(), xml_root.children().end()); + size_t num_regions = std::distance(xml_root.children().begin(), xml_root.children().end()); + /* Reserve memory space for the region */ + fabric_key.reserve_regions(num_regions); + for (size_t iregion = 0; iregion < num_regions; ++iregion) { + fabric_key.create_region(); + } + + /* Reserve memory space for the keys */ + size_t num_keys = 0; + + for (pugi::xml_node xml_region : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_region.name() != std::string("region")) { + bad_tag(xml_region, loc_data, xml_root, {"region"}); + } + num_keys += std::distance(xml_root.children().begin(), xml_root.children().end()); + } + fabric_key.reserve_keys(num_keys); for (size_t ikey = 0; ikey < num_keys; ++ikey) { fabric_key.create_key(); @@ -86,12 +140,12 @@ FabricKey read_xml_fabric_key(const char* key_fname) { /* Iterate over the children under this node, * each child should be named after circuit_model */ - for (pugi::xml_node xml_key : xml_root.children()) { + for (pugi::xml_node xml_region : xml_root.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_key.name() != std::string("key")) { - bad_tag(xml_key, loc_data, xml_root, {"key"}); + if (xml_region.name() != std::string("region")) { + bad_tag(xml_region, loc_data, xml_root, {"region"}); } - read_xml_component_key(xml_key, loc_data, fabric_key); + read_xml_fabric_region(xml_region, loc_data, fabric_key); } } catch (pugiutil::XmlError& e) { archfpga_throw(key_fname, e.line(), diff --git a/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp index 33e345fb9..ea12d75a1 100644 --- a/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp @@ -9,6 +9,8 @@ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" + +/* Headers from openfpga util library */ #include "openfpga_digest.h" /* Headers from arch openfpga library */ @@ -33,7 +35,8 @@ int write_xml_fabric_component_key(std::fstream& fp, return 2; } - fp << "\t" << "\n"; + + /* Write component by component */ + for (const FabricKeyId& key : fabric_key.region_keys(region)) { + err_code = write_xml_fabric_component_key(fp, fabric_key, key); + if (0 != err_code) { + return err_code; + } } + + openfpga::write_tab_to_file(fp, 1); + fp << "" << "\n"; } /* Finish writing the root node */ From 052b8b71c7442bd93d0ca7ed9e05c10e7eaea4e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Sep 2020 20:54:58 -0600 Subject: [PATCH 119/330] [OpenFPGA Tool] Bug fix in the XML parser for fabric regions --- libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp | 2 +- openfpga/src/fabric/fabric_key_writer.cpp | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp index f509ddc79..24e0d8255 100644 --- a/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp @@ -129,7 +129,7 @@ FabricKey read_xml_fabric_key(const char* key_fname) { if (xml_region.name() != std::string("region")) { bad_tag(xml_region, loc_data, xml_root, {"region"}); } - num_keys += std::distance(xml_root.children().begin(), xml_root.children().end()); + num_keys += std::distance(xml_region.children().begin(), xml_region.children().end()); } fabric_key.reserve_keys(num_keys); diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp index 83a83c965..e3920370b 100644 --- a/openfpga/src/fabric/fabric_key_writer.cpp +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -65,6 +65,11 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, num_keys -= 1; } + /* FIXME: create a region for the keys. Later down the road, we will create multiple regions */ + fabric_key.reserve_regions(1); + FabricRegionId region = fabric_key.create_region(); + fabric_key.reserve_region_keys(region, num_keys); + fabric_key.reserve_keys(num_keys); for (size_t ichild = 0; ichild < num_keys; ++ichild) { @@ -78,6 +83,9 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, if (false == module_manager.instance_name(top_module, child_module, child_instance).empty()) { fabric_key.set_key_alias(key, module_manager.instance_name(top_module, child_module, child_instance)); } + + /* Add keys to the region */ + fabric_key.add_key_to_region(region, key); } VTR_LOGV(verbose, From 1e70825383bb364a28dc4d90a4f7270319c13c02 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 13:51:43 -0600 Subject: [PATCH 120/330] [OpenFPGA Tool] Add XML syntax for configurable regions --- libopenfpga/libarchopenfpga/src/config_protocol.cpp | 8 ++++++++ libopenfpga/libarchopenfpga/src/config_protocol.h | 5 +++++ .../libarchopenfpga/src/read_xml_config_protocol.cpp | 10 ++++++++++ 3 files changed, 23 insertions(+) diff --git a/libopenfpga/libarchopenfpga/src/config_protocol.cpp b/libopenfpga/libarchopenfpga/src/config_protocol.cpp index 485297c3a..1499a4baf 100644 --- a/libopenfpga/libarchopenfpga/src/config_protocol.cpp +++ b/libopenfpga/libarchopenfpga/src/config_protocol.cpp @@ -28,6 +28,10 @@ CircuitModelId ConfigProtocol::memory_model() const { return memory_model_; } +int ConfigProtocol::num_regions() const { + return num_regions_; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -42,3 +46,7 @@ void ConfigProtocol::set_memory_model_name(const std::string& memory_model_name) void ConfigProtocol::set_memory_model(const CircuitModelId& memory_model) { memory_model_ = memory_model; } + +void ConfigProtocol::set_num_regions(const int& num_regions) { + num_regions_ = num_regions; +} diff --git a/libopenfpga/libarchopenfpga/src/config_protocol.h b/libopenfpga/libarchopenfpga/src/config_protocol.h index 4915d5bb1..550401098 100644 --- a/libopenfpga/libarchopenfpga/src/config_protocol.h +++ b/libopenfpga/libarchopenfpga/src/config_protocol.h @@ -15,10 +15,12 @@ class ConfigProtocol { e_config_protocol_type type() const; std::string memory_model_name() const; CircuitModelId memory_model() const; + int num_regions() const; public: /* Public Mutators */ void set_type(const e_config_protocol_type& type); void set_memory_model_name(const std::string& memory_model_name); void set_memory_model(const CircuitModelId& memory_model); + void set_num_regions(const int& num_regions); private: /* Internal data */ /* The type of configuration protocol. * In other words, it is about how to organize and access each configurable memory @@ -28,6 +30,9 @@ class ConfigProtocol { /* The circuit model of configuration memory to be used in the protocol */ std::string memory_model_name_; CircuitModelId memory_model_; + + /* Number of configurable regions */ + int num_regions_; }; #endif diff --git a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp index 04833d33a..1cbbb40c0 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -53,8 +53,18 @@ void read_xml_config_organization(pugi::xml_node& xml_config_orgz, config_protocol.set_type(config_orgz_type); + /* Find the circuit model used by the configuration protocol */ config_protocol.set_memory_model_name(get_attribute(xml_config_orgz, "circuit_model_name", loc_data).as_string()); + /* Parse the number of configurable regions + * At least 1 region should be defined, otherwise error out + */ + config_protocol.set_num_regions(get_attribute(xml_config_orgz, "num_regions", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(1)); + if (1 > config_protocol.num_regions()) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_config_orgz), + "Invalid 'num_region=%d' definition. At least 1 region should be defined!\n", + config_protocol.num_regions()); + } } /******************************************************************** From 552dddffd085999ab76ee25a282d17bd8747c0d6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 18:13:07 -0600 Subject: [PATCH 121/330] [OpenFPGA Tool] Support configurable regions in module manager --- openfpga/src/fabric/build_device_module.cpp | 2 +- openfpga/src/fabric/build_top_module.cpp | 12 +- openfpga/src/fabric/build_top_module.h | 3 +- .../src/fabric/build_top_module_memory.cpp | 193 ++++++++++++++---- openfpga/src/fabric/build_top_module_memory.h | 6 +- openfpga/src/fabric/fabric_key_writer.cpp | 40 ++-- openfpga/src/fabric/module_manager.cpp | 131 ++++++++++++ openfpga/src/fabric/module_manager.h | 40 ++++ openfpga/src/fabric/module_manager_fwd.h | 2 + 9 files changed, 358 insertions(+), 71 deletions(-) diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 52e65093c..42919741c 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -120,7 +120,7 @@ int build_device_module_graph(ModuleManager& module_manager, openfpga_ctx.device_rr_gsb(), openfpga_ctx.tile_direct(), openfpga_ctx.arch().arch_direct, - openfpga_ctx.arch().config_protocol.type(), + openfpga_ctx.arch().config_protocol, sram_model, frame_view, compress_routing, duplicate_grid_pin, fabric_key, generate_random_fabric_key); diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 5dd0cf097..d6bb9e263 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -330,7 +330,7 @@ int build_top_module(ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, @@ -396,7 +396,7 @@ int build_top_module(ModuleManager& module_manager, */ if (true == fabric_key.empty()) { organize_top_module_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, + circuit_lib, config_protocol, sram_model, grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); @@ -411,7 +411,7 @@ int build_top_module(ModuleManager& module_manager, /* Shuffle the configurable children in a random sequence */ if (true == generate_random_fabric_key) { - shuffle_top_module_configurable_children(module_manager, top_module); + shuffle_top_module_configurable_children(module_manager, top_module, config_protocol); } /* Add shared SRAM ports from the sub-modules under this Verilog module @@ -427,11 +427,11 @@ int build_top_module(ModuleManager& module_manager, * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type); + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, config_protocol.type()); if (0 < module_num_config_bits) { add_top_module_sram_ports(module_manager, top_module, circuit_lib, sram_model, - sram_orgz_type, module_num_config_bits); + config_protocol.type(), module_num_config_bits); } /* Add module nets to connect memory cells inside @@ -440,7 +440,7 @@ int build_top_module(ModuleManager& module_manager, if (0 < module_manager.configurable_children(top_module).size()) { add_top_module_nets_memory_config_bus(module_manager, decoder_lib, top_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model), + config_protocol.type(), circuit_lib.design_tech_type(sram_model), module_num_config_bits); } diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 6e8e97ef2..6f200973d 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -14,6 +14,7 @@ #include "decoder_library.h" #include "tile_direct.h" #include "arch_direct.h" +#include "config_protocol.h" #include "module_manager.h" #include "io_location_map.h" #include "fabric_key.h" @@ -34,7 +35,7 @@ int build_top_module(ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, const ArchDirect& arch_direct, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 1650b84f3..a7874be5c 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -176,6 +176,94 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager, } } + +/******************************************************************** + * Split memory modules into different configurable regions + * This function will create regions based on the definition + * in the configuration protocols, to accommodate each configurable + * child under the top-level module + * + * For example: + * FPGA Top-level module + * +----------------------+ + * | | | + * | Region 0 | Region 1 | + * | | | + * +----------------------+ + * | | | + * | Region 2 | Region 3 | + * | | | + * +----------------------+ + * + * A typical organization of a Region X + * +-----------------------+ + * | | + * | +------+ +------+ | + * | | | | | | + * | | Tile | | Tile | ... | + * | | | | | | + * | +------+ +------+ | + * | ... ... | + * | | + * | +------+ +------+ | + * | | | | | | + * | | Tile | | Tile | ... | + * | | | | | | + * | +------+ +------+ | + * +-----------------------+ + * + * Note: + * - This function should NOT modify configurable children + * + *******************************************************************/ +static +void build_top_module_configurable_regions(ModuleManager& module_manager, + const ModuleId& top_module, + const ConfigProtocol& config_protocol) { + + /* Ensure we have valid configurable children */ + VTR_ASSERT(false == module_manager.configurable_children(top_module).empty()); + + /* Ensure that our region definition is valid */ + VTR_ASSERT(1 <= config_protocol.num_regions()); + + /* Exclude decoders from the list */ + size_t num_configurable_children = module_manager.configurable_children(top_module).size(); + if (CONFIG_MEM_MEMORY_BANK == config_protocol.type()) { + num_configurable_children -= 2; + } else if (CONFIG_MEM_FRAME_BASED == config_protocol.type()) { + num_configurable_children -= 1; + } + + /* Evenly place each configurable child to each region */ + size_t num_children_per_region = num_configurable_children / config_protocol.num_regions(); + size_t region_child_counter = 0; + bool create_region = true; + ConfigRegionId curr_region = ConfigRegionId::INVALID(); + for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { + if (true == create_region) { + curr_region = module_manager.add_config_region(top_module); + } + + /* Add the child to a region */ + module_manager.add_configurable_child_to_region(top_module, + curr_region, + module_manager.configurable_children(top_module)[ichild], + module_manager.configurable_child_instances(top_module)[ichild]); + + /* See if the current region is full or not: + * For the last region, we will keep adding until we finish all the children + */ + region_child_counter++; + if (region_child_counter < num_children_per_region) { + create_region = false; + } else if (size_t(curr_region) < (size_t)config_protocol.num_regions() - 1) { + create_region = true; + region_child_counter = 0; + } + } +} + /******************************************************************** * Organize the list of memory modules and instances * This function will record all the sub modules of the top-level module @@ -273,7 +361,7 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager, void organize_top_module_memory_modules(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, @@ -332,7 +420,7 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, for (const vtr::Point& io_coord : io_coords[io_side]) { /* Identify the GSB that surrounds the grid */ organize_top_module_tile_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, + circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, @@ -362,12 +450,15 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, for (const vtr::Point& core_coord : core_coords) { organize_top_module_tile_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, + circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, core_coord, NUM_SIDES); } + + /* Split memory modules into different regions */ + build_top_module_configurable_regions(module_manager, top_module, config_protocol); } @@ -375,13 +466,18 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, * Shuffle the configurable children in a random sequence * * TODO: May use a more customized shuffle mechanism + * TODO: Apply region-based shuffling + * The shuffling will be applied to each separated regions + * Configurable children will not shuffled from a region + * to another, instead they should stay in the same region * * Note: * - This function should NOT be called * before allocating any configurable child ********************************************************************/ void shuffle_top_module_configurable_children(ModuleManager& module_manager, - const ModuleId& top_module) { + const ModuleId& top_module, + const ConfigProtocol& config_protocol) { size_t num_keys = module_manager.configurable_children(top_module).size(); std::vector shuffled_keys; shuffled_keys.reserve(num_keys); @@ -403,6 +499,9 @@ void shuffle_top_module_configurable_children(ModuleManager& module_manager, orig_configurable_children[shuffled_keys[ikey]], orig_configurable_child_instances[shuffled_keys[ikey]]); } + + /* Split memory modules into different regions */ + build_top_module_configurable_regions(module_manager, top_module, config_protocol); } /******************************************************************** @@ -421,52 +520,60 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager /* Ensure a clean start */ module_manager.clear_configurable_children(top_module); - for (const FabricKeyId& key : fabric_key.keys()) { - /* Find if instance id is valid */ - std::pair instance_info(ModuleId::INVALID(), 0); - /* If we have an alias, we try to find a instance in this name */ - if (!fabric_key.key_alias(key).empty()) { - /* If we have the key, we can quickly spot instance id. - * Otherwise, we have to exhaustively find the module id and instance id - */ - if (!fabric_key.key_name(key).empty()) { + for (const FabricRegionId& region : fabric_key.regions()) { + /* Create a configurable region in the top module */ + ConfigRegionId top_module_config_region = module_manager.add_config_region(top_module); + for (const FabricKeyId& key : fabric_key.region_keys(region)) { + /* Find if instance id is valid */ + std::pair instance_info(ModuleId::INVALID(), 0); + /* If we have an alias, we try to find a instance in this name */ + if (!fabric_key.key_alias(key).empty()) { + /* If we have the key, we can quickly spot instance id. + * Otherwise, we have to exhaustively find the module id and instance id + */ + if (!fabric_key.key_name(key).empty()) { + instance_info.first = module_manager.find_module(fabric_key.key_name(key)); + instance_info.second = module_manager.instance_id(top_module, instance_info.first, fabric_key.key_alias(key)); + } else { + instance_info = find_module_manager_instance_module_info(module_manager, top_module, fabric_key.key_alias(key)); + } + } else { + /* If we do not have an alias, we use the name and value to build the info deck */ instance_info.first = module_manager.find_module(fabric_key.key_name(key)); - instance_info.second = module_manager.instance_id(top_module, instance_info.first, fabric_key.key_alias(key)); - } else { - instance_info = find_module_manager_instance_module_info(module_manager, top_module, fabric_key.key_alias(key)); + instance_info.second = fabric_key.key_value(key); } - } else { - /* If we do not have an alias, we use the name and value to build the info deck */ - instance_info.first = module_manager.find_module(fabric_key.key_name(key)); - instance_info.second = fabric_key.key_value(key); - } - if (false == module_manager.valid_module_id(instance_info.first)) { - if (!fabric_key.key_alias(key).empty()) { - VTR_LOG_ERROR("Invalid key alias '%s'!\n", - fabric_key.key_alias(key).c_str()); - } else { - VTR_LOG_ERROR("Invalid key name '%s'!\n", - fabric_key.key_name(key).c_str()); + if (false == module_manager.valid_module_id(instance_info.first)) { + if (!fabric_key.key_alias(key).empty()) { + VTR_LOG_ERROR("Invalid key alias '%s'!\n", + fabric_key.key_alias(key).c_str()); + } else { + VTR_LOG_ERROR("Invalid key name '%s'!\n", + fabric_key.key_name(key).c_str()); + } + return CMD_EXEC_FATAL_ERROR; } - return CMD_EXEC_FATAL_ERROR; - } - if (false == module_manager.valid_module_instance_id(top_module, instance_info.first, instance_info.second)) { - if (!fabric_key.key_alias(key).empty()) { - VTR_LOG_ERROR("Invalid key alias '%s'!\n", - fabric_key.key_alias(key).c_str()); - } else { - VTR_LOG_ERROR("Invalid key value '%ld'!\n", - instance_info.second); + if (false == module_manager.valid_module_instance_id(top_module, instance_info.first, instance_info.second)) { + if (!fabric_key.key_alias(key).empty()) { + VTR_LOG_ERROR("Invalid key alias '%s'!\n", + fabric_key.key_alias(key).c_str()); + } else { + VTR_LOG_ERROR("Invalid key value '%ld'!\n", + instance_info.second); + } + return CMD_EXEC_FATAL_ERROR; } - return CMD_EXEC_FATAL_ERROR; - } - /* Now we can add the child to configurable children of the top module */ - module_manager.add_configurable_child(top_module, - instance_info.first, - instance_info.second); + /* Now we can add the child to configurable children of the top module */ + module_manager.add_configurable_child(top_module, + instance_info.first, + instance_info.second); + module_manager.add_configurable_child_to_region(top_module, + top_module_config_region, + instance_info.first, + instance_info.second); + } } return CMD_EXEC_SUCCESS; diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index c4a1ff7f6..f745b9584 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -11,6 +11,7 @@ #include "module_manager.h" #include "circuit_types.h" #include "circuit_library.h" +#include "config_protocol.h" #include "decoder_library.h" #include "device_grid.h" #include "device_rr_gsb.h" @@ -26,7 +27,7 @@ namespace openfpga { void organize_top_module_memory_modules(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, @@ -36,7 +37,8 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, const bool& compact_routing_hierarchy); void shuffle_top_module_configurable_children(ModuleManager& module_manager, - const ModuleId& top_module); + const ModuleId& top_module, + const ConfigProtocol& config_protocol); int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp index e3920370b..82424ef43 100644 --- a/openfpga/src/fabric/fabric_key_writer.cpp +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -65,32 +65,36 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, num_keys -= 1; } - /* FIXME: create a region for the keys. Later down the road, we will create multiple regions */ - fabric_key.reserve_regions(1); - FabricRegionId region = fabric_key.create_region(); - fabric_key.reserve_region_keys(region, num_keys); - fabric_key.reserve_keys(num_keys); - for (size_t ichild = 0; ichild < num_keys; ++ichild) { - ModuleId child_module = module_manager.configurable_children(top_module)[ichild]; - size_t child_instance = module_manager.configurable_child_instances(top_module)[ichild]; + size_t num_regions = module_manager.regions(top_module).size(); + fabric_key.reserve_regions(num_regions); - FabricKeyId key = fabric_key.create_key(); - fabric_key.set_key_name(key, module_manager.module_name(child_module)); - fabric_key.set_key_value(key, child_instance); + /* Create regions for the keys and load keys by region */ + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + FabricRegionId fabric_region = fabric_key.create_region(); + fabric_key.reserve_region_keys(fabric_region, module_manager.region_configurable_children(top_module, config_region).size()); - if (false == module_manager.instance_name(top_module, child_module, child_instance).empty()) { - fabric_key.set_key_alias(key, module_manager.instance_name(top_module, child_module, child_instance)); + for (size_t ichild = 0; ichild < num_keys; ++ichild) { + ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[ichild]; + size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[ichild]; + + FabricKeyId key = fabric_key.create_key(); + fabric_key.set_key_name(key, module_manager.module_name(child_module)); + fabric_key.set_key_value(key, child_instance); + + if (false == module_manager.instance_name(top_module, child_module, child_instance).empty()) { + fabric_key.set_key_alias(key, module_manager.instance_name(top_module, child_module, child_instance)); + } + + /* Add keys to the region */ + fabric_key.add_key_to_region(fabric_region, key); } - - /* Add keys to the region */ - fabric_key.add_key_to_region(region, key); } VTR_LOGV(verbose, - "Created %lu keys for the top module %s.\n", - num_keys, top_module_name.c_str()); + "Created %lu regions and %lu keys for the top module %s.\n", + num_regions, num_keys, top_module_name.c_str()); /* Call the XML writer for fabric key */ int err_code = write_xml_fabric_key(fname.c_str(), fabric_key); diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 139668ea6..283a7a4d9 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -5,6 +5,7 @@ #include #include #include "vtr_assert.h" +#include "vtr_log.h" #include "circuit_library.h" #include "module_manager.h" @@ -97,6 +98,43 @@ ModuleManager::module_net_sink_range ModuleManager::module_net_sinks(const Modul return vtr::make_range(net_sink_ids_[module][net].begin(), net_sink_ids_[module][net].end()); } +ModuleManager::region_range ModuleManager::regions(const ModuleId& module) const { + VTR_ASSERT(valid_module_id(module)); + return vtr::make_range(config_region_ids_[module].begin(), config_region_ids_[module].end()); +} + +std::vector ModuleManager::region_configurable_children(const ModuleId& parent_module, + const ConfigRegionId& region) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + VTR_ASSERT(valid_region_id(parent_module, region)); + + std::vector region_config_children; + region_config_children.reserve(config_region_children_[parent_module][region].size()); + + for (const size_t& child_id : config_region_children_[parent_module][region]) { + region_config_children.push_back(configurable_children_[parent_module][child_id]); + } + + return region_config_children; +} + +std::vector ModuleManager::region_configurable_child_instances(const ModuleId& parent_module, + const ConfigRegionId& region) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + VTR_ASSERT(valid_region_id(parent_module, region)); + + std::vector region_config_child_instances; + region_config_child_instances.reserve(config_region_children_[parent_module][region].size()); + + for (const size_t& child_id : config_region_children_[parent_module][region]) { + region_config_child_instances.push_back(configurable_child_instances_[parent_module][child_id]); + } + + return region_config_child_instances; +} + /****************************************************************************** * Public Accessors ******************************************************************************/ @@ -482,6 +520,10 @@ ModuleId ModuleManager::add_module(const std::string& name) { child_instance_names_.emplace_back(); configurable_children_.emplace_back(); configurable_child_instances_.emplace_back(); + configurable_child_regions_.emplace_back(); + + config_region_ids_.emplace_back(); + config_region_children_.emplace_back(); port_ids_.emplace_back(); ports_.emplace_back(); @@ -661,6 +703,7 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module, configurable_children_[parent_module].push_back(child_module); configurable_child_instances_[parent_module].push_back(child_instance); + configurable_child_regions_[parent_module].push_back(ConfigRegionId::INVALID()); } void ModuleManager::reserve_configurable_child(const ModuleId& parent_module, @@ -673,6 +716,78 @@ void ModuleManager::reserve_configurable_child(const ModuleId& parent_module, if (num_children > configurable_child_instances_[parent_module].size()) { configurable_child_instances_[parent_module].reserve(num_children); } + if (num_children > configurable_child_instances_[parent_module].size()) { + configurable_child_regions_[parent_module].reserve(num_children); + } +} + +ConfigRegionId ModuleManager::add_config_region(const ModuleId& module) { + /* Validate the module id */ + VTR_ASSERT ( valid_module_id(module) ); + + /* Create an new id */ + ConfigRegionId config_region_id = ConfigRegionId(config_region_ids_[module].size()); + config_region_ids_[module].push_back(config_region_id); + + config_region_children_[module].emplace_back(); + + return config_region_id; +} + +void ModuleManager::add_configurable_child_to_region(const ModuleId& parent_module, + const ConfigRegionId& config_region, + const ModuleId& child_module, + const size_t& child_instance) { + /* Validate the module id */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + VTR_ASSERT ( valid_region_id(parent_module, config_region) ); + + /* Ensure that the child module is in the configurable children list */ + size_t config_child_id = configurable_children(parent_module).size(); + for (size_t ichild = 0; ichild < configurable_children(parent_module).size(); ++ichild) { + if ( (child_module == configurable_children(parent_module)[ichild]) + && (child_instance == configurable_child_instances(parent_module)[ichild]) ) { + config_child_id = ichild; + break; + } + } + + /* Error out as the child is not valid */ + if (config_child_id == configurable_children(parent_module).size()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Try to add an invalid configurable child '%s[%lu]' to region '%lu'!\n", + module_name(child_module).c_str(), + child_instance, + size_t(config_region)); + exit(1); + } + + /* If the child is already in another region, error out */ + if (config_region != configurable_child_regions_[parent_module][config_child_id]) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Try to add a configurable child '%s[%lu]' to region '%lu' which is already added to another region '%lu'!\n", + module_name(child_module).c_str(), + child_instance, + size_t(config_region), + size_t(configurable_child_regions_[parent_module][config_child_id])); + exit(1); + } + + /* Ensure that the child is not in the list */ + if (config_region_children_[parent_module][config_region].end() != std::find(config_region_children_[parent_module][config_region].begin(), + config_region_children_[parent_module][config_region].end(), + config_child_id)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "The configurable child '%s[%lu]' is already in the region '%lu'! Skip adding\n", + module_name(child_module).c_str(), + child_instance, + size_t(config_region)); + return; + } + + /* Passed all the checks, add the child to the region */ + config_region_children_[parent_module][config_region].push_back(config_child_id); } void ModuleManager::reserve_module_nets(const ModuleId& module, @@ -869,6 +984,14 @@ void ModuleManager::clear_configurable_children(const ModuleId& parent_module) { configurable_children_[parent_module].clear(); configurable_child_instances_[parent_module].clear(); + configurable_child_regions_[parent_module].clear(); +} + +void ModuleManager::clear_config_region(const ModuleId& parent_module) { + VTR_ASSERT(valid_module_id(parent_module)); + + config_region_ids_[parent_module].clear(); + config_region_children_[parent_module].clear(); } /****************************************************************************** @@ -902,6 +1025,14 @@ bool ModuleManager::valid_module_instance_id(const ModuleId& parent_module, return ( instance_id < num_instance(parent_module, child_module) ); } +bool ModuleManager::valid_region_id(const ModuleId& module, + const ConfigRegionId& region) const { + if (false == valid_module_id(module)) { + return false; + } + return ( size_t(region) < config_region_ids_[module].size() ) && ( region == config_region_ids_[module][region] ); +} + void ModuleManager::invalidate_name2id_map() { name_id_map_.clear(); } diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index 9827e296f..23ed75ead 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -124,12 +124,14 @@ class ModuleManager { typedef lazy_id_iterator module_net_iterator; typedef vtr::vector::const_iterator module_net_src_iterator; typedef vtr::vector::const_iterator module_net_sink_iterator; + typedef vtr::vector::const_iterator region_iterator; typedef vtr::Range module_range; typedef vtr::Range module_port_range; typedef vtr::Range module_net_range; typedef vtr::Range module_net_src_range; typedef vtr::Range module_net_sink_range; + typedef vtr::Range region_range; public: /* Public aggregators */ /* Find all the modules */ @@ -151,6 +153,15 @@ class ModuleManager { /* Find the sink ids of modules */ module_net_sink_range module_net_sinks(const ModuleId& module, const ModuleNetId& net) const; + /* Find all the regions */ + region_range regions(const ModuleId& module) const; + /* Find all the configurable child modules under a region of a parent module */ + std::vector region_configurable_children(const ModuleId& parent_module, + const ConfigRegionId& region) const; + /* Find all the instances of configurable child modules under a region of a parent module */ + std::vector region_configurable_child_instances(const ModuleId& parent_module, + const ConfigRegionId& region) const; + public: /* Public accessors */ size_t num_modules() const; size_t num_nets(const ModuleId& module) const; @@ -242,6 +253,18 @@ class ModuleManager { */ void reserve_configurable_child(const ModuleId& module, const size_t& num_children); + /* Create a new configurable region under a module */ + ConfigRegionId add_config_region(const ModuleId& module); + /* Add a configurable child module to a region + * Note: + * - The child module must be added as a configurable child to the parent module + * before calling this function! + */ + void add_configurable_child_to_region(const ModuleId& parent_module, + const ConfigRegionId& config_region, + const ModuleId& child_module, + const size_t& child_instance); + /* Reserved a number of module nets for a given module * for memory efficiency */ @@ -281,6 +304,13 @@ class ModuleManager { * Do NOT use unless you know what you are doing!!! */ void clear_configurable_children(const ModuleId& parent_module); + + /* This is a strong function which will remove all the configurable regions + * under a given parent module + * It is mainly used by loading fabric keys + * Do NOT use unless you know what you are doing!!! + */ + void clear_config_region(const ModuleId& parent_module); public: /* Public validators/invalidators */ bool valid_module_id(const ModuleId& module) const; bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; @@ -288,6 +318,8 @@ class ModuleManager { bool valid_module_instance_id(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id) const; + bool valid_region_id(const ModuleId& module, + const ConfigRegionId& region) const; private: /* Private validators/invalidators */ void invalidate_name2id_map(); void invalidate_port_lookup(); @@ -310,6 +342,14 @@ class ModuleManager { */ vtr::vector> configurable_children_; /* Child modules with configurable memory bits that this module contain */ vtr::vector> configurable_child_instances_; /* Instances of child modules with configurable memory bits that this module contain */ + vtr::vector> configurable_child_regions_; /* Instances of child modules with configurable memory bits that this module contain */ + + /* Configurable regions to group the configurable children + * Note: + * - Each child can only be added a group + */ + vtr::vector> config_region_ids_; + vtr::vector>> config_region_children_; /* Port-level data */ vtr::vector> port_ids_; /* List of ports for each Module */ diff --git a/openfpga/src/fabric/module_manager_fwd.h b/openfpga/src/fabric/module_manager_fwd.h index 695ce1024..5aea7f71f 100644 --- a/openfpga/src/fabric/module_manager_fwd.h +++ b/openfpga/src/fabric/module_manager_fwd.h @@ -19,6 +19,7 @@ struct module_pin_id_tag; struct module_net_id_tag; struct module_net_src_id_tag; struct module_net_sink_id_tag; +struct config_region_id_tag; typedef vtr::StrongId ModuleId; typedef vtr::StrongId InstanceId; @@ -27,6 +28,7 @@ typedef vtr::StrongId ModulePinId; typedef vtr::StrongId ModuleNetId; typedef vtr::StrongId ModuleNetSrcId; typedef vtr::StrongId ModuleNetSinkId; +typedef vtr::StrongId ConfigRegionId; class ModuleManager; From f93d46a870e2e480583dc1618fae218d141224a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 19:03:19 -0600 Subject: [PATCH 122/330] [OpenFPGA Tool] Add multiple configuration chain support in top module builder --- openfpga/src/fabric/build_top_module.cpp | 4 +- .../src/fabric/build_top_module_memory.cpp | 175 ++++++++++++++++-- openfpga/src/fabric/build_top_module_memory.h | 5 +- 3 files changed, 169 insertions(+), 15 deletions(-) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index d6bb9e263..95d1c7dce 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -431,7 +431,7 @@ int build_top_module(ModuleManager& module_manager, if (0 < module_num_config_bits) { add_top_module_sram_ports(module_manager, top_module, circuit_lib, sram_model, - config_protocol.type(), module_num_config_bits); + config_protocol, module_num_config_bits); } /* Add module nets to connect memory cells inside @@ -440,7 +440,7 @@ int build_top_module(ModuleManager& module_manager, if (0 < module_manager.configurable_children(top_module).size()) { add_top_module_nets_memory_config_bus(module_manager, decoder_lib, top_module, - config_protocol.type(), circuit_lib.design_tech_type(sram_model), + config_protocol, circuit_lib.design_tech_type(sram_model), module_num_config_bits); } diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index a7874be5c..444591d6b 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -579,6 +579,41 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Generate a list of ports that are used for SRAM configuration + * to the top-level module + * 1. Standalone SRAMs: + * use the suggested port_size + * 2. Scan-chain Flip-flops: + * IMPORTANT: the port size will be limited by the number of configurable regions + * 3. Memory decoders: + * use the suggested port_size + ********************************************************************/ +static +size_t generate_top_module_sram_port_size(const ConfigProtocol& config_protocol, + const size_t& num_config_bits) { + size_t sram_port_size = num_config_bits; + + switch (config_protocol.type()) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: + /* CCFF head/tail are single-bit ports */ + sram_port_size = config_protocol.num_regions(); + break; + case CONFIG_MEM_MEMORY_BANK: + break; + case CONFIG_MEM_FRAME_BASED: + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid type of SRAM organization!\n"); + exit(1); + } + + return sram_port_size; +} + /******************************************************************** * Add a list of ports that are used for SRAM configuration to the FPGA * top-level module @@ -606,13 +641,13 @@ void add_top_module_sram_ports(ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, + const ConfigProtocol& config_protocol, const size_t& num_config_bits) { - std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); - size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); + std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, config_protocol.type()); + size_t sram_port_size = generate_top_module_sram_port_size(config_protocol, num_config_bits); /* Add ports to the module manager */ - switch (sram_orgz_type) { + switch (config_protocol.type()) { case CONFIG_MEM_STANDALONE: { for (const std::string& sram_port_name : sram_port_names) { /* Add generated ports to the ModuleManager */ @@ -928,6 +963,124 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag module_manager.add_configurable_child(top_module, wl_decoder_module, 0); } +/******************************************************************** + * Connect all the memory modules under the parent module in a chain + * + * Region 0: + * +--------+ +--------+ +--------+ + * ccff_head[0] --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail[0] + * | Module | | Module | | Module | + * | [0] | | [1] | | [N-1] | + * +--------+ +--------+ +--------+ + * + * Region 1: + * +--------+ +--------+ +--------+ + * ccff_head[1] --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail[1] + * | Module | | Module | | Module | + * | [0] | | [1] | | [N-1] | + * +--------+ +--------+ +--------+ + * + * For the 1st memory module: + * net source is the configuration chain head of the primitive module + * net sink is the configuration chain head of the next memory module + * + * For the rest of memory modules: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain head of the next memory module + *********************************************************************/ +static +void add_top_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const ConfigProtocol& config_protocol) { + for (const ConfigRegionId& config_region : module_manager.regions(parent_module)) { + for (size_t mem_index = 0; mem_index < module_manager.region_configurable_children(parent_module, config_region).size(); ++mem_index) { + ModuleId net_src_module_id; + size_t net_src_instance_id; + ModulePortId net_src_port_id; + size_t net_src_pin_id; + + ModuleId net_sink_module_id; + size_t net_sink_instance_id; + ModulePortId net_sink_port_id; + size_t net_sink_pin_id; + + if (0 == mem_index) { + /* Find the port name of configuration chain head */ + std::string src_port_name = generate_sram_port_name(config_protocol.type(), CIRCUIT_MODEL_PORT_INPUT); + net_src_module_id = parent_module; + net_src_instance_id = 0; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + net_src_pin_id = size_t(config_region); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index]; + net_sink_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + net_sink_pin_id = 0; + } else { + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + net_src_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index - 1]; + net_src_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index - 1]; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + net_src_pin_id = 0; + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index]; + net_sink_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + net_sink_pin_id = 0; + } + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + + VTR_ASSERT(net_src_pin_id < net_src_port.get_width()); + VTR_ASSERT(net_sink_pin_id < net_sink_port.get_width()); + + /* Create a net and add source and sink to it */ + ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[net_src_pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]); + } + + /* For the last memory module: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain tail of the primitive module + */ + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + ModuleId net_src_module_id = module_manager.region_configurable_children(parent_module, config_region).back(); + size_t net_src_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region).back(); + ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + size_t net_src_pin_id = 0; + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_sram_port_name(config_protocol.type(), CIRCUIT_MODEL_PORT_OUTPUT); + ModuleId net_sink_module_id = parent_module; + size_t net_sink_instance_id = 0; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + size_t net_sink_pin_id = size_t(config_region); + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + + VTR_ASSERT(net_src_pin_id < net_src_port.get_width()); + VTR_ASSERT(net_sink_pin_id < net_sink_port.get_width()); + + /* Create a net and add source and sink to it */ + ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[net_src_pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]); + } +} + /********************************************************************* * Add the port-to-port connection between all the memory modules * and their parent module @@ -976,17 +1129,17 @@ static void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& parent_module, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const size_t& num_config_bits) { - switch (sram_orgz_type) { + switch (config_protocol.type()) { case CONFIG_MEM_STANDALONE: add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module, - sram_orgz_type, CIRCUIT_MODEL_PORT_BL); + config_protocol.type(), CIRCUIT_MODEL_PORT_BL); add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module, - sram_orgz_type, CIRCUIT_MODEL_PORT_WL); + config_protocol.type(), CIRCUIT_MODEL_PORT_WL); break; case CONFIG_MEM_SCAN_CHAIN: { - add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, CONFIG_MEM_SCAN_CHAIN); + add_top_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, config_protocol); break; } case CONFIG_MEM_MEMORY_BANK: @@ -1037,7 +1190,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& parent_module, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const e_circuit_model_design_tech& mem_tech, const size_t& num_config_bits) { @@ -1047,7 +1200,7 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, case CIRCUIT_MODEL_DESIGN_CMOS: add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib, parent_module, - sram_orgz_type, + config_protocol, num_config_bits); break; case CIRCUIT_MODEL_DESIGN_RRAM: diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index f745b9584..87ca278cd 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -16,6 +16,7 @@ #include "device_grid.h" #include "device_rr_gsb.h" #include "fabric_key.h" +#include "config_protocol.h" /******************************************************************** * Function declaration @@ -48,13 +49,13 @@ void add_top_module_sram_ports(ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, + const ConfigProtocol& config_protocol, const size_t& num_config_bits); void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& parent_module, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const e_circuit_model_design_tech& mem_tech, const size_t& num_config_bits); From 47f3c799270238d906195f28aa0efaeefbfeabcf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 19:08:19 -0600 Subject: [PATCH 123/330] [OpenFPGA Tool] Bug fix in module manager due to configurable regions --- openfpga/src/fabric/module_manager.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 283a7a4d9..dd3c070fa 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -764,7 +764,8 @@ void ModuleManager::add_configurable_child_to_region(const ModuleId& parent_modu } /* If the child is already in another region, error out */ - if (config_region != configurable_child_regions_[parent_module][config_child_id]) { + if ( (true == valid_region_id(parent_module, configurable_child_regions_[parent_module][config_child_id])) + && (config_region != configurable_child_regions_[parent_module][config_child_id]) ) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Try to add a configurable child '%s[%lu]' to region '%lu' which is already added to another region '%lu'!\n", module_name(child_module).c_str(), From e179a58b155a115706899447d40092e696c8c565 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 20:42:18 -0600 Subject: [PATCH 124/330] [OpenFPGA Tool] Bug fix for long runtime --- openfpga/src/base/openfpga_build_fabric.cpp | 1 - .../src/fabric/build_top_module_memory.cpp | 19 +++++++--- openfpga/src/fabric/fabric_key_writer.cpp | 10 +----- openfpga/src/fabric/fabric_key_writer.h | 1 - openfpga/src/fabric/module_manager.cpp | 35 +++---------------- openfpga/src/fabric/module_manager.h | 3 +- 6 files changed, 22 insertions(+), 47 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index 3b1472e88..a0b909ccf 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -122,7 +122,6 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, VTR_ASSERT(false == fkey_fname.empty()); curr_status = write_fabric_key_to_xml_file(openfpga_ctx.module_graph(), fkey_fname, - openfpga_ctx.arch().config_protocol.type(), cmd_context.option_enable(cmd, opt_verbose)); /* If there is any error, final status cannot be overwritten by a success flag */ if (CMD_EXEC_SUCCESS != curr_status) { diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 444591d6b..f8b1894ab 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -221,6 +221,8 @@ void build_top_module_configurable_regions(ModuleManager& module_manager, const ModuleId& top_module, const ConfigProtocol& config_protocol) { + vtr::ScopedStartFinishTimer timer("Build configurable regions for the top module"); + /* Ensure we have valid configurable children */ VTR_ASSERT(false == module_manager.configurable_children(top_module).empty()); @@ -240,7 +242,7 @@ void build_top_module_configurable_regions(ModuleManager& module_manager, size_t region_child_counter = 0; bool create_region = true; ConfigRegionId curr_region = ConfigRegionId::INVALID(); - for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { + for (size_t ichild = 0; ichild < module_manager.configurable_children(top_module).size(); ++ichild) { if (true == create_region) { curr_region = module_manager.add_config_region(top_module); } @@ -249,7 +251,8 @@ void build_top_module_configurable_regions(ModuleManager& module_manager, module_manager.add_configurable_child_to_region(top_module, curr_region, module_manager.configurable_children(top_module)[ichild], - module_manager.configurable_child_instances(top_module)[ichild]); + module_manager.configurable_child_instances(top_module)[ichild], + ichild); /* See if the current region is full or not: * For the last region, we will keep adding until we finish all the children @@ -262,6 +265,9 @@ void build_top_module_configurable_regions(ModuleManager& module_manager, region_child_counter = 0; } } + + /* Ensure that the number of configurable regions created matches the definition */ + VTR_ASSERT((size_t)config_protocol.num_regions() == module_manager.regions(top_module).size()); } /******************************************************************** @@ -500,7 +506,8 @@ void shuffle_top_module_configurable_children(ModuleManager& module_manager, orig_configurable_child_instances[shuffled_keys[ikey]]); } - /* Split memory modules into different regions */ + /* Reset configurable regions */ + module_manager.clear_config_region(top_module); build_top_module_configurable_regions(module_manager, top_module, config_protocol); } @@ -520,6 +527,8 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager /* Ensure a clean start */ module_manager.clear_configurable_children(top_module); + size_t curr_configurable_child_id = 0; + for (const FabricRegionId& region : fabric_key.regions()) { /* Create a configurable region in the top module */ ConfigRegionId top_module_config_region = module_manager.add_config_region(top_module); @@ -572,7 +581,9 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager module_manager.add_configurable_child_to_region(top_module, top_module_config_region, instance_info.first, - instance_info.second); + instance_info.second, + curr_configurable_child_id); + curr_configurable_child_id++; } } diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp index 82424ef43..63202ea90 100644 --- a/openfpga/src/fabric/fabric_key_writer.cpp +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -29,7 +29,6 @@ namespace openfpga { ***************************************************************************************/ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, const std::string& fname, - const e_config_protocol_type& config_protocol_type, const bool& verbose) { std::string timer_message = std::string("Write fabric key to XML file '") + fname + std::string("'"); @@ -58,13 +57,6 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, FabricKey fabric_key; size_t num_keys = module_manager.configurable_children(top_module).size(); - /* Exclude configuration-related modules in the keys */ - if (CONFIG_MEM_MEMORY_BANK == config_protocol_type) { - num_keys -= 2; - } else if (CONFIG_MEM_FRAME_BASED == config_protocol_type) { - num_keys -= 1; - } - fabric_key.reserve_keys(num_keys); size_t num_regions = module_manager.regions(top_module).size(); @@ -75,7 +67,7 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, FabricRegionId fabric_region = fabric_key.create_region(); fabric_key.reserve_region_keys(fabric_region, module_manager.region_configurable_children(top_module, config_region).size()); - for (size_t ichild = 0; ichild < num_keys; ++ichild) { + for (size_t ichild = 0; ichild < module_manager.region_configurable_children(top_module, config_region).size(); ++ichild) { ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[ichild]; size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[ichild]; diff --git a/openfpga/src/fabric/fabric_key_writer.h b/openfpga/src/fabric/fabric_key_writer.h index 3062db15a..68e6468b2 100644 --- a/openfpga/src/fabric/fabric_key_writer.h +++ b/openfpga/src/fabric/fabric_key_writer.h @@ -16,7 +16,6 @@ namespace openfpga { int write_fabric_key_to_xml_file(const ModuleManager& module_manager, const std::string& fname, - const e_config_protocol_type& config_protocol_type, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index dd3c070fa..d888d1a2f 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -737,31 +737,16 @@ ConfigRegionId ModuleManager::add_config_region(const ModuleId& module) { void ModuleManager::add_configurable_child_to_region(const ModuleId& parent_module, const ConfigRegionId& config_region, const ModuleId& child_module, - const size_t& child_instance) { + const size_t& child_instance, + const size_t& config_child_id) { /* Validate the module id */ VTR_ASSERT ( valid_module_id(parent_module) ); VTR_ASSERT ( valid_module_id(child_module) ); VTR_ASSERT ( valid_region_id(parent_module, config_region) ); /* Ensure that the child module is in the configurable children list */ - size_t config_child_id = configurable_children(parent_module).size(); - for (size_t ichild = 0; ichild < configurable_children(parent_module).size(); ++ichild) { - if ( (child_module == configurable_children(parent_module)[ichild]) - && (child_instance == configurable_child_instances(parent_module)[ichild]) ) { - config_child_id = ichild; - break; - } - } - - /* Error out as the child is not valid */ - if (config_child_id == configurable_children(parent_module).size()) { - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Try to add an invalid configurable child '%s[%lu]' to region '%lu'!\n", - module_name(child_module).c_str(), - child_instance, - size_t(config_region)); - exit(1); - } + VTR_ASSERT(child_module == configurable_children(parent_module)[config_child_id]); + VTR_ASSERT(child_instance == configurable_child_instances(parent_module)[config_child_id]); /* If the child is already in another region, error out */ if ( (true == valid_region_id(parent_module, configurable_child_regions_[parent_module][config_child_id])) @@ -775,18 +760,6 @@ void ModuleManager::add_configurable_child_to_region(const ModuleId& parent_modu exit(1); } - /* Ensure that the child is not in the list */ - if (config_region_children_[parent_module][config_region].end() != std::find(config_region_children_[parent_module][config_region].begin(), - config_region_children_[parent_module][config_region].end(), - config_child_id)) { - VTR_LOGF_ERROR(__FILE__, __LINE__, - "The configurable child '%s[%lu]' is already in the region '%lu'! Skip adding\n", - module_name(child_module).c_str(), - child_instance, - size_t(config_region)); - return; - } - /* Passed all the checks, add the child to the region */ config_region_children_[parent_module][config_region].push_back(config_child_id); } diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index 23ed75ead..9f39b23db 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -263,7 +263,8 @@ class ModuleManager { void add_configurable_child_to_region(const ModuleId& parent_module, const ConfigRegionId& config_region, const ModuleId& child_module, - const size_t& child_instance); + const size_t& child_instance, + const size_t& config_child_id); /* Reserved a number of module nets for a given module * for memory efficiency From 180d72f3e5503add15d9bd53c0bbc88238908b24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Sep 2020 21:04:08 -0600 Subject: [PATCH 125/330] [Tool] Add regions to fabric bitstream --- .../src/fpga_bitstream/fabric_bitstream.cpp | 62 ++++++++++++++----- .../src/fpga_bitstream/fabric_bitstream.h | 21 ++++++- .../src/fpga_bitstream/fabric_bitstream_fwd.h | 2 + 3 files changed, 70 insertions(+), 15 deletions(-) diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp index 750cc0296..b395a7984 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp @@ -18,6 +18,9 @@ FabricBitstream::FabricBitstream() { invalid_bit_ids_.clear(); address_length_ = 0; wl_address_length_ = 0; + + num_regions_ = 0; + invalid_region_ids_.clear(); } /************************************************** @@ -33,6 +36,23 @@ FabricBitstream::fabric_bit_range FabricBitstream::bits() const { fabric_bit_iterator(FabricBitId(num_bits_), invalid_bit_ids_)); } +size_t FabricBitstream::num_regions() const { + return num_regions_; +} + +/* Find all the configuration bits */ +FabricBitstream::fabric_bit_region_range FabricBitstream::regions() const { + return vtr::make_range(fabric_bit_region_iterator(FabricBitRegionId(0), invalid_region_ids_), + fabric_bit_region_iterator(FabricBitRegionId(num_regions_), invalid_region_ids_)); +} + +std::vector FabricBitstream::region_bits(const FabricBitRegionId& region_id) const { + /* Ensure a valid id */ + VTR_ASSERT(true == valid_region_id(region_id)); + + return region_bits_[region_id]; +} + /****************************************************************************** * Public Accessors ******************************************************************************/ @@ -134,19 +154,6 @@ void FabricBitstream::set_bit_din(const FabricBitId& bit_id, bit_dins_[bit_id] = din; } -void FabricBitstream::reverse() { - std::reverse(config_bit_ids_.begin(), config_bit_ids_.end()); - - if (true == use_address_) { - std::reverse(bit_addresses_.begin(), bit_addresses_.end()); - std::reverse(bit_dins_.begin(), bit_dins_.end()); - - if (true == use_wl_address_) { - std::reverse(bit_wl_addresses_.begin(), bit_wl_addresses_.end()); - } - } -} - void FabricBitstream::set_use_address(const bool& enable) { /* Add a lock, only can be modified when num bits are zero*/ if (0 == num_bits_) { @@ -177,11 +184,38 @@ void FabricBitstream::set_wl_address_length(const size_t& length) { } } +void FabricBitstream::reserve_regions(const size_t& num_regions) { + region_bits_.reserve(num_regions); +} + +void FabricBitstream::reverse() { + std::reverse(config_bit_ids_.begin(), config_bit_ids_.end()); + + if (true == use_address_) { + std::reverse(bit_addresses_.begin(), bit_addresses_.end()); + std::reverse(bit_dins_.begin(), bit_dins_.end()); + + if (true == use_wl_address_) { + std::reverse(bit_wl_addresses_.begin(), bit_wl_addresses_.end()); + } + } +} + +void FabricBitstream::reverse_region_bits(const FabricBitRegionId& region_id) { + VTR_ASSERT(true == valid_region_id(region_id)); + + std::reverse(region_bits_[region_id].begin(), region_bits_[region_id].end()); +} + /****************************************************************************** * Public Validators ******************************************************************************/ -char FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const { +bool FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const { return (size_t(bit_id) < num_bits_); } +bool FabricBitstream::valid_region_id(const FabricBitRegionId& region_id) const { + return (size_t(region_id) < num_regions_); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h index 9869fffed..2521babc5 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h @@ -93,8 +93,10 @@ class FabricBitstream { class lazy_id_iterator; typedef lazy_id_iterator fabric_bit_iterator; + typedef lazy_id_iterator fabric_bit_region_iterator; typedef vtr::Range fabric_bit_range; + typedef vtr::Range fabric_bit_region_range; public: /* Public constructor */ FabricBitstream(); @@ -104,6 +106,11 @@ class FabricBitstream { size_t num_bits() const; fabric_bit_range bits() const; + /* Find all the configuration regions */ + size_t num_regions() const; + fabric_bit_region_range regions() const; + std::vector region_bits(const FabricBitRegionId& region_id) const; + public: /* Public Accessors */ /* Find the configuration bit id in architecture bitstream database */ ConfigBitId config_bit(const FabricBitId& bit_id) const; @@ -139,6 +146,12 @@ class FabricBitstream { void set_bit_din(const FabricBitId& bit_id, const char& din); + /* Reserve regions */ + void reserve_regions(const size_t& num_regions); + + /* Reserve bits by region */ + void reverse_region_bits(const FabricBitRegionId& region_id); + /* Reverse bit sequence of the fabric bitstream * This is required by configuration chain protocol */ @@ -162,9 +175,15 @@ class FabricBitstream { void set_wl_address_length(const size_t& length); public: /* Public Validators */ - char valid_bit_id(const FabricBitId& bit_id) const; + bool valid_bit_id(const FabricBitId& bit_id) const; + bool valid_region_id(const FabricBitRegionId& bit_id) const; private: /* Internal data */ + /* Unique id of a region in the Bitstream */ + size_t num_regions_; + std::unordered_set invalid_region_ids_; + vtr::vector> region_bits_; + /* Unique id of a bit in the Bitstream */ size_t num_bits_; std::unordered_set invalid_bit_ids_; diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h b/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h index d93eec638..bc0a87beb 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h +++ b/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h @@ -13,8 +13,10 @@ namespace openfpga { /* Strong Ids for BitstreamContext */ struct fabric_bit_id_tag; +struct fabric_bit_region_id_tag; typedef vtr::StrongId FabricBitId; +typedef vtr::StrongId FabricBitRegionId; class FabricBitstream; From e988e35f814bf1f5506e2b6292463a9ae58aa24a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 12:22:10 -0600 Subject: [PATCH 126/330] [Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches --- .../fpga_bitstream/build_fabric_bitstream.cpp | 91 +++++++++---- .../src/fpga_bitstream/fabric_bitstream.cpp | 23 +++- .../src/fpga_bitstream/fabric_bitstream.h | 8 +- .../fpga_verilog/verilog_top_testbench.cpp | 124 +++++++++++++----- openfpga/src/utils/fabric_bitstream_utils.cpp | 67 ++++++++++ openfpga/src/utils/fabric_bitstream_utils.h | 29 ++++ 6 files changed, 278 insertions(+), 64 deletions(-) create mode 100644 openfpga/src/utils/fabric_bitstream_utils.cpp create mode 100644 openfpga/src/utils/fabric_bitstream_utils.h diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index 05e93d22a..adbcf53fd 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -38,29 +38,58 @@ static void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& bitstream_manager, const ConfigBlockId& parent_block, const ModuleManager& module_manager, + const ModuleId& top_module, const ModuleId& parent_module, - FabricBitstream& fabric_bitstream) { + const ConfigRegionId& config_region, + FabricBitstream& fabric_bitstream, + const FabricBitRegionId& fabric_bitstream_region) { /* Depth-first search: if we have any children in the parent_block, * we dive to the next level first! */ if (0 < bitstream_manager.block_children(parent_block).size()) { - for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) { - ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; - size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; - /* Get the instance name and ensure it is not empty */ - std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); - - /* Find the child block that matches the instance name! */ - ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); - /* We must have one valid block id! */ - if (true != bitstream_manager.valid_block_id(child_block)) - VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + if (parent_module == top_module) { + for (size_t child_id = 0; child_id < module_manager.region_configurable_children(parent_module, config_region).size(); ++child_id) { + ModuleId child_module = module_manager.region_configurable_children(parent_module, config_region)[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; + /* Get the instance name and ensure it is not empty */ + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + + /* Find the child block that matches the instance name! */ + ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); + /* We must have one valid block id! */ + if (true != bitstream_manager.valid_block_id(child_block)) + VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); - /* Go recursively */ - rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, child_block, - module_manager, child_module, - fabric_bitstream); + /* Go recursively */ + rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, child_block, + module_manager, top_module, + child_module, + config_region, + fabric_bitstream, + fabric_bitstream_region); + } + } else { + for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) { + ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; + size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; + /* Get the instance name and ensure it is not empty */ + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + + /* Find the child block that matches the instance name! */ + ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); + /* We must have one valid block id! */ + if (true != bitstream_manager.valid_block_id(child_block)) + VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + + /* Go recursively */ + rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, child_block, + module_manager, top_module, + child_module, + config_region, + fabric_bitstream, + fabric_bitstream_region); + } } /* Ensure that there should be no configuration bits in the parent block */ VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); @@ -71,7 +100,8 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b * And then, we can return */ for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) { - fabric_bitstream.add_bit(config_bit); + FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit); + fabric_bitstream.add_bit_to_region(fabric_bitstream_region, fabric_bit); } } @@ -382,19 +412,32 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc /* Reserve bits before build-up */ fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); - rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block, - module_manager, top_module, - fabric_bitstream); + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); + rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block, + module_manager, top_module, + top_module, + config_region, + fabric_bitstream, + fabric_bitstream_region); + } + break; } case CONFIG_MEM_SCAN_CHAIN: { /* Reserve bits before build-up */ fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); - rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block, - module_manager, top_module, - fabric_bitstream); - fabric_bitstream.reverse(); + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); + rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block, + module_manager, top_module, + top_module, + config_region, + fabric_bitstream, + fabric_bitstream_region); + fabric_bitstream.reverse_region_bits(fabric_bitstream_region); + } break; } case CONFIG_MEM_MEMORY_BANK: { diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp index b395a7984..5949a0bfb 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp @@ -50,7 +50,7 @@ std::vector FabricBitstream::region_bits(const FabricBitRegionId& r /* Ensure a valid id */ VTR_ASSERT(true == valid_region_id(region_id)); - return region_bits_[region_id]; + return region_bit_ids_[region_id]; } /****************************************************************************** @@ -185,7 +185,24 @@ void FabricBitstream::set_wl_address_length(const size_t& length) { } void FabricBitstream::reserve_regions(const size_t& num_regions) { - region_bits_.reserve(num_regions); + region_bit_ids_.reserve(num_regions); +} + +FabricBitRegionId FabricBitstream::add_region() { + FabricBitRegionId region = FabricBitRegionId(num_regions_); + /* Add a new bit, and allocate associated data structures */ + num_regions_++; + region_bit_ids_.emplace_back(); + + return region; +} + +void FabricBitstream::add_bit_to_region(const FabricBitRegionId& region_id, + const FabricBitId& bit_id) { + VTR_ASSERT(true == valid_region_id(region_id)); + VTR_ASSERT(true == valid_bit_id(bit_id)); + + region_bit_ids_[region_id].push_back(bit_id); } void FabricBitstream::reverse() { @@ -204,7 +221,7 @@ void FabricBitstream::reverse() { void FabricBitstream::reverse_region_bits(const FabricBitRegionId& region_id) { VTR_ASSERT(true == valid_region_id(region_id)); - std::reverse(region_bits_[region_id].begin(), region_bits_[region_id].end()); + std::reverse(region_bit_ids_[region_id].begin(), region_bit_ids_[region_id].end()); } /****************************************************************************** diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h index 2521babc5..0761ff7c2 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h @@ -149,6 +149,12 @@ class FabricBitstream { /* Reserve regions */ void reserve_regions(const size_t& num_regions); + /* Add a new configuration region */ + FabricBitRegionId add_region(); + + void add_bit_to_region(const FabricBitRegionId& region_id, + const FabricBitId& bit_id); + /* Reserve bits by region */ void reverse_region_bits(const FabricBitRegionId& region_id); @@ -182,7 +188,7 @@ class FabricBitstream { /* Unique id of a region in the Bitstream */ size_t num_regions_; std::unordered_set invalid_region_ids_; - vtr::vector> region_bits_; + vtr::vector> region_bit_ids_; /* Unique id of a bit in the Bitstream */ size_t num_bits_; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 2d957b6b6..a5a6e1f82 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -23,6 +23,8 @@ #include "simulation_utils.h" #include "openfpga_atom_netlist_utils.h" +#include "fabric_bitstream_utils.h" + #include "verilog_constants.h" #include "verilog_writer_utils.h" #include "verilog_testbench_utils.h" @@ -136,18 +138,22 @@ void print_verilog_top_testbench_flatten_memory_port(std::fstream& fp, * Print local wires for configuration chain protocols *******************************************************************/ static -void print_verilog_top_testbench_config_chain_port(std::fstream& fp) { +void print_verilog_top_testbench_config_chain_port(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module) { /* Validate the file stream */ valid_file_stream(fp); /* Print the head of configuraion-chains here */ print_verilog_comment(fp, std::string("---- Configuration-chain head -----")); - BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); + ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); + BasicPort config_chain_head_port = module_manager.module_port(top_module, cc_head_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_head_port) << ";" << std::endl; /* Print the tail of configuration-chains here */ print_verilog_comment(fp, std::string("---- Configuration-chain tail -----")); - BasicPort config_chain_tail_port(generate_configuration_chain_tail_name(), 1); + ModulePortId cc_tail_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_tail_name()); + BasicPort config_chain_tail_port = module_manager.module_port(top_module, cc_tail_port_id); fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl; } @@ -271,7 +277,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module); break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_config_chain_port(fp); + print_verilog_top_testbench_config_chain_port(fp, module_manager, top_module); break; case CONFIG_MEM_MEMORY_BANK: print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); @@ -659,7 +665,10 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { - size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits(); + /* Find the longest regional bitstream */ + size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); + + size_t num_config_clock_cycles = 1 + regional_bitstream_max_size; /* Branch on the type of configuration protocol */ switch (sram_orgz_type) { @@ -670,23 +679,24 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz num_config_clock_cycles = 2; break; case CONFIG_MEM_SCAN_CHAIN: - /* For fast configuraiton, the bitstream size counts from the first bit '1' */ + /* For fast configuration, the bitstream size counts from the first bit '1' */ if (true == fast_configuration) { - size_t full_num_config_clock_cycles = num_config_clock_cycles; - size_t num_bits_to_skip = 0; - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - break; - } - num_bits_to_skip++; - } + /* For fast configuration, the number of bits to be skipped + * depends on each regional bitstream + * For example: + * Region 0: 000000001111101010 + * Region 1: 00000011010101 + * Region 2: 0010101111000110 + * The number of bits that can be skipped is limited by Region 2 + */ + size_t num_bits_to_skip = find_configuration_chain_fabric_bitstream_size_to_be_skipped(fabric_bitstream, bitstream_manager, bit_value_to_skip); - num_config_clock_cycles = full_num_config_clock_cycles - num_bits_to_skip; + num_config_clock_cycles = 1 + regional_bitstream_max_size - num_bits_to_skip; VTR_LOG("Fast configuration reduces number of configuration clock cycles from %lu to %lu (compression_rate = %f%)\n", - full_num_config_clock_cycles, + 1 + regional_bitstream_max_size, num_config_clock_cycles, - 100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.)); + 100. * ((float)num_config_clock_cycles / (float)(1 + regional_bitstream_max_size) - 1.)); } break; case CONFIG_MEM_MEMORY_BANK: @@ -770,14 +780,17 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, * During each programming cycle, we feed the input of scan chain with a memory bit *******************************************************************/ static -void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp) { +void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module) { /* Validate the file stream */ valid_file_stream(fp); BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - BasicPort cc_head_port(generate_configuration_chain_head_name(), 1); - BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), 1); + ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); + BasicPort cc_head_port = module_manager.module_port(top_module, cc_head_port_id); + BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), cc_head_port.get_width()); /* Add an empty line as splitter */ fp << std::endl; @@ -962,7 +975,9 @@ void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp, /* No need to have a specific task. Loading is done in 1 clock cycle */ break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp); + print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp, + module_manager, + top_module); break; case CONFIG_MEM_MEMORY_BANK: print_verilog_top_testbench_load_bitstream_task_memory_bank(fp, @@ -1359,6 +1374,8 @@ static void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, const bool& fast_configuration, const bool& bit_value_to_skip, + const ModuleManager& module_manager, + const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ @@ -1370,7 +1387,8 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, * We do not care the value of scan_chain head during the first programming cycle * It is reset anyway */ - BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); + ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); + BasicPort config_chain_head_port = module_manager.module_port(top_module, cc_head_port_id); std::vector initial_values(config_chain_head_port.get_width(), 0); print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); @@ -1383,27 +1401,60 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << std::endl; + /* Find the longest bitstream */ + size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); + + /* For fast configuration, the bitstream size counts from the first bit '1' */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = find_configuration_chain_fabric_bitstream_size_to_be_skipped(fabric_bitstream, bitstream_manager, bit_value_to_skip); + } + VTR_ASSERT(num_bits_to_skip < regional_bitstream_max_size); + + /* Reorganize the regional bitstreams to be the same size */ + std::vector> regional_bitstreams; + regional_bitstreams.reserve(fabric_bitstream.regions().size()); + for (const FabricBitRegionId& region : fabric_bitstream.regions()) { + std::vector curr_regional_bitstream; + curr_regional_bitstream.resize(regional_bitstream_max_size, false); + /* Starting index should consider the offset between the current bitstream size and + * the maximum size of regional bitstream + */ + size_t offset = regional_bitstream_max_size - fabric_bitstream.region_bits(region).size(); + for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { + curr_regional_bitstream[offset] = bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)); + offset++; + } + VTR_ASSERT(offset == regional_bitstream_max_size); + + /* Add the adapt sub-bitstream */ + regional_bitstreams.push_back(curr_regional_bitstream); + } /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) + * + * Note that bitstream may come from different regions + * The bitstream value to be loaded should be organized as follows + * + * cycleA + * | + * Region 0: 0|00000001111101010 + * Region 1: | 00000011010101 + * Region 2: | 0010101111000110 + * + * Zero bits will be added to the head of those bitstreams are shorter + * than the longest bitstream */ - bool start_config = false; - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if ( (false == start_config) - && (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { - start_config = true; - } - - /* In fast configuration mode, we do not output anything - * until we have to (the first bit '1' detected) - */ - if ( (true == fast_configuration) - && (false == start_config)) { - continue; + for (size_t ibit = num_bits_to_skip; ibit < regional_bitstream_max_size; ++ibit) { + std::vector curr_cc_head_val; + curr_cc_head_val.reserve(fabric_bitstream.regions().size()); + for (const auto& region_bitstream : regional_bitstreams) { + curr_cc_head_val.push_back((size_t)region_bitstream[ibit]); } fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); - fp << "(1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)) << ");" << std::endl; + fp << "(" << generate_verilog_constant_values(curr_cc_head_val) << ");" << std::endl; } /* Raise the flag of configuration done when bitstream loading is complete */ @@ -1654,6 +1705,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, case CONFIG_MEM_SCAN_CHAIN: print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, bit_value_to_skip, + module_manager, top_module, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp new file mode 100644 index 000000000..53d99d5a1 --- /dev/null +++ b/openfpga/src/utils/fabric_bitstream_utils.cpp @@ -0,0 +1,67 @@ +/************************************************************************ + * Function to perform fundamental operation for fabric bitstream class + * These functions are not universal methods for the FabricBitstream class + * They are made to ease the development in some specific purposes + * Please classify such functions in this file + ***********************************************************************/ + +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "fabric_bitstream_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Find the longest bitstream size of a fabric bitstream + *******************************************************************/ +size_t find_fabric_regional_bitstream_max_size(const FabricBitstream& fabric_bitstream) { + size_t regional_bitstream_max_size = 0; + /* Find the longest regional bitstream */ + for (const auto& region : fabric_bitstream.regions()) { + if (regional_bitstream_max_size < fabric_bitstream.region_bits(region).size()) { + regional_bitstream_max_size = fabric_bitstream.region_bits(region).size(); + } + } + return regional_bitstream_max_size; +} + +/******************************************************************** + * For fast configuration, the number of bits to be skipped + * depends on each regional bitstream + * For example: + * Region 0: 000000001111101010 + * Region 1: 00000011010101 + * Region 2: 0010101111000110 + * The number of bits that can be skipped is limited by Region 2 + * Find the longest bitstream size of a fabric bitstream + *******************************************************************/ +size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(const FabricBitstream& fabric_bitstream, + const BitstreamManager& bitstream_manager, + const bool& bit_value_to_skip) { + size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); + + size_t num_bits_to_skip = size_t(-1); + for (const auto& region : fabric_bitstream.regions()) { + size_t curr_region_num_bits_to_skip = 0; + for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { + if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + curr_region_num_bits_to_skip++; + } + /* For regional bitstream which is short than the longest region bitstream, + * The number of bits to skip + */ + curr_region_num_bits_to_skip += regional_bitstream_max_size - fabric_bitstream.region_bits(region).size(); + num_bits_to_skip = std::min(curr_region_num_bits_to_skip, num_bits_to_skip); + } + + return num_bits_to_skip; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/fabric_bitstream_utils.h b/openfpga/src/utils/fabric_bitstream_utils.h new file mode 100644 index 000000000..998332ccf --- /dev/null +++ b/openfpga/src/utils/fabric_bitstream_utils.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Header file for fabric_bitstream_utils.cpp + *******************************************************************/ +#ifndef FABRIC_BITSTREAM_UTILS_H +#define FABRIC_BITSTREAM_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "bitstream_manager.h" +#include "fabric_bitstream.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +size_t find_fabric_regional_bitstream_max_size(const FabricBitstream& fabric_bitstream); + +size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(const FabricBitstream& fabric_bitstream, + const BitstreamManager& bitstream_manager, + const bool& bit_value_to_skip); + +} /* end namespace openfpga */ + +#endif From e0d7bcfa11b57a356c58d1a1b4b8c231f40ec403 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 12:49:32 -0600 Subject: [PATCH 127/330] [Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols --- .../fpga_bitstream/build_fabric_bitstream.cpp | 59 +++++++++++++------ 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index adbcf53fd..4c05a5389 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -131,7 +131,8 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana const size_t& num_bls, const size_t& num_wls, size_t& cur_mem_index, - FabricBitstream& fabric_bitstream) { + FabricBitstream& fabric_bitstream, + const FabricBitRegionId& fabric_bitstream_region) { /* Depth-first search: if we have any children in the parent_block, * we dive to the next level first! @@ -171,7 +172,8 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana bl_addr_size, wl_addr_size, num_bls, num_wls, cur_mem_index, - fabric_bitstream); + fabric_bitstream, + fabric_bitstream_region); } /* Ensure that there should be no configuration bits in the parent block */ VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); @@ -203,6 +205,9 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana /* Set data input */ fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit)); + /* Add the bit to the region */ + fabric_bitstream.add_bit_to_region(fabric_bitstream_region, fabric_bit); + /* Increase the memory index */ cur_mem_index++; } @@ -237,7 +242,8 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b const ModuleManager& module_manager, const std::vector& parent_modules, const std::vector& addr_code, - FabricBitstream& fabric_bitstream) { + FabricBitstream& fabric_bitstream, + FabricBitRegionId& fabric_bitstream_region) { /* Depth-first search: if we have any children in the parent_block, * we dive to the next level first! @@ -355,7 +361,8 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager, child_blocks, module_manager, child_modules, child_addr_code, - fabric_bitstream); + fabric_bitstream, + fabric_bitstream_region); } /* Ensure that there should be no configuration bits in the parent block */ VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); @@ -392,6 +399,9 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b /* Set data input */ fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit)); + + /* Add the bit to the region */ + fabric_bitstream.add_bit_to_region(fabric_bitstream_region, fabric_bit); } } @@ -472,13 +482,21 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc fabric_bitstream.set_wl_address_length(wl_addr_port_info.get_width()); fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); - rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block, - module_manager, top_module, top_module, - bl_addr_port_info.get_width(), - wl_addr_port_info.get_width(), - bl_port_info.get_width(), - wl_port_info.get_width(), - cur_mem_index, fabric_bitstream); + /* TODO: Currently only support 1 region. Will expand later! */ + VTR_ASSERT(1 == module_manager.regions(top_module).size()); + + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); + rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block, + module_manager, top_module, top_module, + bl_addr_port_info.get_width(), + wl_addr_port_info.get_width(), + bl_port_info.get_width(), + wl_port_info.get_width(), + cur_mem_index, + fabric_bitstream, + fabric_bitstream_region); + } break; } case CONFIG_MEM_FRAME_BASED: { @@ -492,12 +510,19 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); fabric_bitstream.set_address_length(addr_port_info.get_width()); - rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager, - std::vector(1, top_block), - module_manager, - std::vector(1, top_module), - std::vector(), - fabric_bitstream); + /* TODO: Currently only support 1 region. Will expand later! */ + VTR_ASSERT(1 == module_manager.regions(top_module).size()); + + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); + rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager, + std::vector(1, top_block), + module_manager, + std::vector(1, top_module), + std::vector(), + fabric_bitstream, + fabric_bitstream_region); + } break; } default: From 23449dc5c3cca301080d03a00805281133975ee8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 13:46:40 -0600 Subject: [PATCH 128/330] [Architecture] Add multiple region configuration chain architecture --- .../k4_N4_40nm_multi_region_cc_openfpga.xml | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml new file mode 100644 index 000000000..bbb33c21b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 5be5835b7198259fd33acacf072ff027cafb65cf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 13:48:39 -0600 Subject: [PATCH 129/330] [Regression Test] Add multiple region configuration chain test case --- .../config/task.conf | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf new file mode 100644 index 000000000..6aa293777 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From d5c74113998950474d551525397367b7dd619afd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 13:50:31 -0600 Subject: [PATCH 130/330] [Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain --- ..._region_cc_use_both_set_reset_openfpga.xml | 191 ++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..1cefcf3b5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From a0d1d68402b668bc3727744f95bf97a1c0d5891a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 13:53:41 -0600 Subject: [PATCH 131/330] [Regression Test] Add regression tests for smart fast configuration chain using multiple regions --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf new file mode 100644 index 000000000..2e2c32b55 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 6e8ebd797994653eb2f7371d533907108346886c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 13:57:31 -0600 Subject: [PATCH 132/330] [Regression Tests] Deploy multi-region test cases to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index f84af4b37..4549424d3 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -17,9 +17,11 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From 462886fb5fd6e3a1b3734224a8afa091ee7675e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:02:03 -0600 Subject: [PATCH 133/330] [Documentation] Update documentation for the multiple region support on configuration chain --- docs/source/manual/arch_lang/config_protocol.rst | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index 48fd66ac3..6c76c5663 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -49,7 +49,7 @@ It will use the circuit model defined in :numref:`fig_ccff`. .. code-block:: xml - + .. _fig_ccff_fpga: @@ -60,6 +60,10 @@ It will use the circuit model defined in :numref:`fig_ccff`. Example of a configuration chain to program core logic of a FPGA +.. option:: num_regions="" + + Specify the number of configuration chains to be used across the fabrics. By default, it will be only 1 configuration chain. The more configuration chain to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics. + Frame-based Example ~~~~~~~~~~~~~~~~~~~ The following XML code describes frame-based memory banks to configure the core logic of FPGA. From 02ea639959ecb7ecf56d33d4334f2182d7130359 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:13:38 -0600 Subject: [PATCH 134/330] [Regression Test] Add test for fabric key based on multiple region --- .../config/task.conf | 34 ++++++++++++++++ .../config/task.conf | 39 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf create mode 100644 openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf new file mode 100644 index 000000000..a89cf8eaa --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf new file mode 100644 index 000000000..0b6f18163 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 4f00d310d3011a660ce38698343e5b7a4fff56a8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:14:50 -0600 Subject: [PATCH 135/330] [Architecture] Add example fabric key using multiple regions --- .../k4_N4_2x2_multi_region_sample_key.xml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml diff --git a/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml b/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml new file mode 100644 index 000000000..33e632b84 --- /dev/null +++ b/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + From ff6570df9d99156db6b9dfeae8957dde3d7d61ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:19:40 -0600 Subject: [PATCH 136/330] [Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI --- .travis/fpga_verilog_reg_test.sh | 2 ++ .../load_external_key_multi_region_cc_fpga/config/task.conf | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index ce8c57b92..e7582360d 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -84,8 +84,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --sho echo -e "Testing Secured FPGA fabrics"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs echo -e "Testing Power-gating designs"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf index 0b6f18163..bfaecd8a1 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml -openfpga_vpr_device_layout=2x2 +openfpga_vpr_device_layout=auto [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml From d4d02ab16ae5b4ee8a1d18864abf665d949ff9aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:22:23 -0600 Subject: [PATCH 137/330] [Regression Test] Move fabric key tests to basic tests --- .travis/basic_reg_test.sh | 9 +++++++++ .travis/fpga_verilog_reg_test.sh | 6 ------ .../generate_multi_region_vanilla_key/config/task.conf | 0 .../fabric_key/generate_random_key/config/task.conf | 0 .../fabric_key/generate_vanilla_key/config/task.conf | 0 .../fabric_key/load_external_key/config/task.conf | 0 .../load_external_key_cc_fpga/config/task.conf | 0 .../config/task.conf | 0 8 files changed, 9 insertions(+), 6 deletions(-) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_multi_region_vanilla_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_random_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_vanilla_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key_cc_fpga/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf (100%) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 4549424d3..8f5961618 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -66,6 +66,15 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench -- echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs +echo -e "Testing Secured FPGA fabrics"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs + + echo -e "Testing K4 series FPGA"; echo -e "Testing K4N4 with facturable LUTs"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index e7582360d..08278e98a 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -82,12 +82,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin echo -e "Testing Verilog generation with spy output pads"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs -echo -e "Testing Secured FPGA fabrics"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs echo -e "Testing Power-gating designs"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf From 639d57016b0f48db92abae1a6569cca4378cad28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 15:55:42 -0600 Subject: [PATCH 138/330] [Documentation] Update documentation about the multi-region configuration --- .../manual/arch_lang/config_protocol.rst | 9 +- docs/source/manual/arch_lang/fabric_key.rst | 207 ++++++++++++------ .../figures/fabric_key_motivation.png | Bin 0 -> 170919 bytes .../figures/multi_region_config_chains.png | Bin 0 -> 23890 bytes 4 files changed, 143 insertions(+), 73 deletions(-) create mode 100644 docs/source/manual/arch_lang/figures/fabric_key_motivation.png create mode 100644 docs/source/manual/arch_lang/figures/multi_region_config_chains.png diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index 6c76c5663..a460ad1de 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -62,7 +62,14 @@ It will use the circuit model defined in :numref:`fig_ccff`. .. option:: num_regions="" - Specify the number of configuration chains to be used across the fabrics. By default, it will be only 1 configuration chain. The more configuration chain to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics. + Specify the number of configuration chains to be used across the fabrics. By default, it will be only 1 configuration chain. The more configuration chain to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics. The organization of each configurable region can be customized through the fabric key (see details in :ref:`fabric_key`). + +.. figure:: figures/multi_region_config_chains.png + :scale: 100% + :alt: map to buried treasure + + Examples of single- and multiple- region configuration chains + Frame-based Example ~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/fabric_key.rst b/docs/source/manual/arch_lang/fabric_key.rst index 4e0086aeb..81a45fa37 100644 --- a/docs/source/manual/arch_lang/fabric_key.rst +++ b/docs/source/manual/arch_lang/fabric_key.rst @@ -1,3 +1,5 @@ +.. _fabric_key: + Fabric Key ~~~~~~~~~~ @@ -6,6 +8,12 @@ With this key, OpenFPGA can generate correct bitstreams for the FPGA. Using a wrong key, OpenFPGA may error out or generate wrong bitstreams. The fabric key support allows users to build secured/classified FPGA chips even with an open-source tool. +.. figure:: figures/fabric_key_motivation.png + :scale: 60% + :alt: map to buried treasure + + The use of fabric key to secure the FPGA chip design + .. note:: Users are the only owner of the key. OpenFPGA will not store or replicate the key. Key Generation @@ -19,7 +27,56 @@ A fabric key can be achieved in the following ways: File Format ``````````` -A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable memory blocks in the top-level FPGA fabric: +A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable blocks in the top-level FPGA fabric. + +Configurable Region +^^^^^^^^^^^^^^^^^^^ + +The top-level FPGA fabric can consist of several configurable regions, where a region may contain one or multiple configurable blocks. Each configurable region can be configured independently and in parrallel. + +.. option:: + + - ``id`` indicates the unique id of a configurable region in the fabric. + + .. warning:: The id must start from zero! + + .. note:: The number of regions defined in the fabric key must be consistent with the number of regions defined in the configuration protocol of architecture description. (See details in :ref:`config_protocol`). + +The following example shows how to define multiple configuration regions in the fabric key. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + +Configurable Block +^^^^^^^^^^^^^^^^^^^ + +Each configurable block is defined as a key. There are two ways to define a key, either with alias or with name and value. + +.. option:: - ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric. @@ -29,86 +86,92 @@ A fabric key follows an XML format. As shown in the following XML code, the key - ``alias`` indicates the instance name of the configurable memory block in the top-level FPGA fabric. If a valid alias is specified, the ``name`` and ``value`` are not required. -.. note:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key. +.. warning:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key. The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. This key contains only ``alias`` which is easy to craft. .. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. This key contains only ``name`` and ``value`` which is fast to parse. .. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/fabric_key_motivation.png b/docs/source/manual/arch_lang/figures/fabric_key_motivation.png new file mode 100644 index 0000000000000000000000000000000000000000..7ebb0f820e5f6c69f0625f76f9232c1d34a82670 GIT binary patch literal 170919 zcmdqJ^;cV8&@Y@22o$HdQ(THWMT={3cP$imCuy-@HtaCE6$M(!VpUFpcHF+#_GIRg{fTgG)qX__jU;qG8FB%we1<(Eq zJz@ZQXv)6^)QwZ@A-?$9=quW)ssdOM=V$izo|t*$U7VtD4NVBi4& z5I_HW0PXUp5o}8W6lJ8eeSwE2DE9;dcT{A^iq8@`fP}cw>d!P%o?{YxXy`bw8=AP^ zGdt8J(0D1ytxf>c=#hN=T2fQ8q=fu&!lUh?>+{3$+R^IKm}sD0$p24LSW5d#=N6>g8~1CT**M56{S8WSHdsIiVtgvw1y5LEyj0k%jIfB>lV zFdlO!zbl}D?D|;-kY3AIS_u0s_zR0p+A$yKzHaB*Z92i8KGfN%yx0>az^P%C-79lHkZ|$-li6uHP+VFcqrwTanZZblFpx)HxWHErGSC3NPt%iX+Vg(` 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zd963bka#zh6^Dvsnld25UP3dzoBBt09BW1rX1UyM3(cK_v*#5v&e=%tbojNOF4TP7 zzM0*PiU|KC#zg%Z7mnAzLucoIR!zyFK$h)&P3PLE*K1;oGQlXIZFCzxV}@LxhVzm)^g3GOx+}b$r^5-Y|N3S)`3C-gCUaVWaN< iSmXbnmcUkAJ_%N%X)ikc)(HD66W4yAuU@Tc7y3V3%HhHQ literal 0 HcmV?d00001 From 6817c045c2da1548b69697db199c4e1937fd641e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 16:24:52 -0600 Subject: [PATCH 139/330] [Documentation] Update tutorial about tooling --- docs/source/tutorials/eda_flow.rst | 18 ------- docs/source/tutorials/figures/eda_flow.png | Bin 274359 -> 0 bytes .../tutorials/figures/openfpga_tools.png | Bin 0 -> 837476 bytes docs/source/tutorials/index.rst | 2 +- docs/source/tutorials/tools.rst | 47 ++++++++++++++++++ 5 files changed, 48 insertions(+), 19 deletions(-) delete mode 100644 docs/source/tutorials/eda_flow.rst delete mode 100644 docs/source/tutorials/figures/eda_flow.png create mode 100644 docs/source/tutorials/figures/openfpga_tools.png create mode 100644 docs/source/tutorials/tools.rst diff --git a/docs/source/tutorials/eda_flow.rst b/docs/source/tutorials/eda_flow.rst deleted file mode 100644 index 31cffa0ca..000000000 --- a/docs/source/tutorials/eda_flow.rst +++ /dev/null @@ -1,18 +0,0 @@ -.. _eda_flow: - -Supported EDA flows in OpenFPGA -------------------------------- - -As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis requires the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in "Tools Guide>Extended Architecture Description Language"). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results when enabled by command-line options. (See each "FPGA-*Branch*" about command-line options available) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See "FPGA-SPICE... > Create Customized SPICE Modules" for guidelines in customizing your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e., HSPICE, can be called to conduct a power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See "FPGA-SPICE... > Run SPICE simulation"). - -.. _fig_eda_flow: - -.. figure:: ./figures/eda_flow.png - :scale: 50% - :alt: map to buried treasure - - Detailed EDA flows based on FPGA-SPICE/Verilog/Bitstream in the purpose of (a) architecture of the output of FPGA-SPICE (b) functionality verification; (c) prototyping and area analysis and (d) power analysis. *TBD: change for Yosys* - -FPGA-Verilog is the part of the flow in charge of the Verilog and the semi-custom design flow. In our case, we use Cadence Innovus. The goal is to get the full-FPGA layout to complete the analysis provided by FPGA-SPICE. By having the layout, we can get an area analysis on the one hand and have new information concerning the power analysis. For instance, having the layout allows the user to have new information on the circuit such as the parasitics. - -FPGA-Bitstream is the part of the flow in charge of the functional verification of the produced FPGA. Testbenches are generated by FPGA-Verilog and are combined with the full FPGA fabric in Modelsim. A bitstream is generated at the same time as the testbenches. This bitstream configures the FPGA with the functionality given by the user to VPR at the beginning of the flow. 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purposes, OpenFPGA integrates several tools to i.e., FPGA-Verilog, FPGA-SDC and FPGA-bitstream (highlighted green in :ref:`fig_openfpga_tools`, with other popular open-source EDA tools, i.e., VPR and Yosys. + +.. _fig_openfpga_tools: + +.. figure:: figures/openfpga_tools.png + :scale: 25% + :alt: map to buried treasure + + OpenFPGA tool suites and design flows + +Third-Party Tools +^^^^^^^^^^^^^^^^^ + +OpenFPGA accepts and outputs in standard file formats, and therefore can +interface a wide range of commercial and open-source tools. + ++--------------+-------------------------+ +| Usage | Tools | ++==============+=========================+ +| Backend | Synopsys IC Compiler II | +| | | +| | Cadence Innovus | ++--------------+-------------------------+ +| Timing | Synopsys PrimeTime | +| Analyzer | | +| | Cadence Tempus | ++--------------+-------------------------+ +| Verification | Synopsys VCS | +| | | +| | Synopsys Formality | +| | | +| | Mentor ModelSim | +| | | +| | Mentor QuestaSim | +| | | +| | Cadence NCSim | +| | | +| | Icarus iVerilog | ++--------------+-------------------------+ From 67300af9870cef0b7377272cc02674f88e4e581e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 16:52:16 -0600 Subject: [PATCH 140/330] [Documentation] Update motivation with new set of figures --- docs/source/figures/fpga_sdc_motivation.png | Bin 0 -> 280238 bytes .../figures/fpga_verilog_motivation.png | Bin 0 -> 204406 bytes .../figures/openfpga_arch_lang_coverage.png | Bin 0 -> 1399467 bytes .../fpga_verilog/figures/preconfig_module.png | Bin 26664 -> 306063 bytes docs/source/manual/fpga_verilog/testbench.rst | 2 +- docs/source/motivation.rst | 44 +++++++++++++++++- 6 files changed, 44 insertions(+), 2 deletions(-) create mode 100644 docs/source/figures/fpga_sdc_motivation.png create mode 100644 docs/source/figures/fpga_verilog_motivation.png create mode 100644 docs/source/figures/openfpga_arch_lang_coverage.png diff --git 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z_a`M6K!%@OwI}#g%gjRfWB*)I$o-Qgvz7GV33FO2^X9*!+yCL}{SMU;{|8X7LW=+Z diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index 728adb1e0..1be9ec688 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -88,7 +88,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n .. _fig_preconfig_module: .. figure:: ./figures/preconfig_module.png - :scale: 100% + :scale: 25% Internal structure of a pre-configured FPGA module diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst index b70b92ace..7fc461b83 100644 --- a/docs/source/motivation.rst +++ b/docs/source/motivation.rst @@ -27,12 +27,43 @@ The rest of this section will focus on detailed motivation on each of them, as d Design flows in different purposes using OpenFPGA +Fully Customizable Architecture +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +OpenFPGA supports VPR's architecture description language, which allows +users to define versatile programmable fabrics down to point-to-point +interconnection. +OpenFPGA leverage VPR's architecture description by introducing an XML-based +architecture annotation, enabling fully customizable FPGA fabric down to +circuit elements. +As illustrated in :ref:`fig_openfpga_arch_lang_coverage`, OpenFPGA's +architecture annotation covers a complete FPGA fabric, including both the +programmable fabric and the configuration peripheral. + +.. _fig_openfpga_arch_lang_coverage: + +.. figure:: ./figures/openfpga_arch_lang_coverage.png + :scale: 15% + :alt: OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation + + OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation + +The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`. FPGA-Verilog ~~~~~~~~~~~~ Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. +FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabling various backend choices, as illustrated in :ref:`fig_fpga_verilog_motivation`. + +.. _fig_fpga_verilog_motivation: + +.. figure:: ./figures/fpga_verilog_motivation.png + :scale: 25% + :alt: Flexible netlist format support by FPGA-Verilog to enable various backend choices + + FPGA-Verilog enabling flexible backend flows The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`. @@ -41,7 +72,18 @@ FPGA-SDC Design constraints are indepensible in modern ASIC design flows to guarantee the performance level. OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis. -Our flow automatically generates two sets of SDC files. The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage. +Our flow automatically generates two sets of SDC files. +- The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. OpenFPGA allows users to define timing constraints in the architecture description and outputs timing constraints in standard format, enabling fully timing constrained backend flow (see :ref:`fig_fpga_sdc_motivation`). +- The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage. + +.. _fig_fpga_sdc_motivation: + +.. figure:: ./figures/fpga_sdc_motivation.png + :scale: 25% + :alt: FPGA-SDC enabling iterative timing constrained backend flow + + FPGA-SDC enabling iterative timing constrained backend flow + The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`. From 2d92a1f1af7b854436caf89d88b475a4b7152028 Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Fri, 2 Oct 2020 10:18:10 -0400 Subject: [PATCH 141/330] Edits to enable basic run_fpga_flow.py --- openfpga_flow/misc/fpgaflow_default_tool_path.conf | 6 +++--- openfpga_flow/scripts/run_fpga_flow.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 5b89052e3..ec5d4db6b 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -7,11 +7,11 @@ odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc -vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr +vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog -include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists +include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists [FLOW_SCRIPT_CONFIG] valid_flows = standard,vpr_blif,vtr,vtr_standard,yosys_vpr @@ -68,4 +68,4 @@ vvp_output=vvp_sim_output.txt [CMD_ARGUMENT_DEPENDANCY] vpr_fpga_verilog=vpr_fpga_verilog_dir|abc -vpr_fpga_verilog_dir=vpr_fpga_verilog \ No newline at end of file +vpr_fpga_verilog_dir=vpr_fpga_verilog diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a331d506d..46b242a75 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -672,7 +672,7 @@ def run_vpr(): min_channel_width) extract_vpr_stats(args.top_module+"_fr_chan_width_vpr.txt") else: - extract_vpr_stats(args.top_module+"_min_chan_width.txt") + extract_vpr_stats(args.top_module+"_min_chan_width_vpr.txt") if args.power: extract_vpr_stats(logfile=args.top_module+".power", r_filename="vpr_power_stat", @@ -716,11 +716,11 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): "--net_file", args.top_module+"_vpr.net", "--place_file", args.top_module+"_vpr.place", "--route_file", args.top_module+"_vpr.route", - "--full_stats", + "--full_stats", "on", "--activity_file", args.top_module+"_ace_out.act", ] if not args.disp: - command += ["--nodisp"] + command += ["--disp", "off"] if route_only: command += ["--route"] # Power options From 02e21d115b318dc3423ba87ebe93a9cceed7fddd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 10:00:12 -0600 Subject: [PATCH 142/330] [Documentation] Update 3-rd party tool version requirements --- docs/source/tutorials/tools.rst | 48 +++++++++++++++++---------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/docs/source/tutorials/tools.rst b/docs/source/tutorials/tools.rst index 0d22041d3..c332d602a 100644 --- a/docs/source/tutorials/tools.rst +++ b/docs/source/tutorials/tools.rst @@ -22,26 +22,28 @@ Third-Party Tools OpenFPGA accepts and outputs in standard file formats, and therefore can interface a wide range of commercial and open-source tools. -+--------------+-------------------------+ -| Usage | Tools | -+==============+=========================+ -| Backend | Synopsys IC Compiler II | -| | | -| | Cadence Innovus | -+--------------+-------------------------+ -| Timing | Synopsys PrimeTime | -| Analyzer | | -| | Cadence Tempus | -+--------------+-------------------------+ -| Verification | Synopsys VCS | -| | | -| | Synopsys Formality | -| | | -| | Mentor ModelSim | -| | | -| | Mentor QuestaSim | -| | | -| | Cadence NCSim | -| | | -| | Icarus iVerilog | -+--------------+-------------------------+ ++--------------+-------------------------+---------------------+ +| Usage | Tools | Version Requirement | ++==============+=========================+=====================+ +| Backend | Synopsys IC Compiler II | v2019.03 or later | +| | | | +| | Cadence Innovus | v19.1 or later | ++--------------+-------------------------+---------------------+ +| Timing | Synopsys PrimeTime | v2019.03 or later | +| Analyzer | | | +| | Cadence Tempus | v19.15 or later | ++--------------+-------------------------+---------------------+ +| Verification | Synopsys VCS | v2019.06 or later | +| | | | +| | Synopsys Formality | v2019.03 or later | +| | | | +| | Mentor ModelSim | v10.6 or later | +| | | | +| | Mentor QuestaSim | v2019.3 or later | +| | | | +| | Cadence NCSim | v15.2 or later | +| | | | +| | Icarus iVerilog | v10.1 or later | ++--------------+-------------------------+---------------------+ + +* The version requirements is based on our local tests. Older versions may work. From 113708c68f0b1ed408fd0f41c0b7365c9f943057 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 11:56:10 -0600 Subject: [PATCH 143/330] [Documentation] Reorganization the overview part by adding technical highlights --- docs/source/index.rst | 5 +- docs/source/manual/fpga_verilog/testbench.rst | 10 ++ .../openfpga_shell/launch_openfpga_shell.rst | 2 - .../{ => overview}/figures/OpenFPGA_logo.pdf | Bin .../{ => overview}/figures/OpenFPGA_logo.png | Bin .../figures/fpga_sdc_motivation.png | Bin .../figures/fpga_verilog_motivation.png | Bin .../figures/openfpga_arch_lang_coverage.png | Bin .../{ => overview}/figures/openfpga_flow.png | Bin .../figures/openfpga_motivation.png | Bin docs/source/overview/index.rst | 9 ++ docs/source/{ => overview}/motivation.rst | 0 docs/source/overview/tech_highlights.rst | 90 ++++++++++++++++++ 13 files changed, 112 insertions(+), 4 deletions(-) rename docs/source/{ => overview}/figures/OpenFPGA_logo.pdf (100%) rename docs/source/{ => overview}/figures/OpenFPGA_logo.png (100%) rename docs/source/{ => overview}/figures/fpga_sdc_motivation.png (100%) rename docs/source/{ => overview}/figures/fpga_verilog_motivation.png (100%) rename docs/source/{ => overview}/figures/openfpga_arch_lang_coverage.png (100%) rename docs/source/{ => overview}/figures/openfpga_flow.png (100%) rename docs/source/{ => overview}/figures/openfpga_motivation.png (100%) create mode 100644 docs/source/overview/index.rst rename docs/source/{ => overview}/motivation.rst (100%) create mode 100644 docs/source/overview/tech_highlights.rst diff --git a/docs/source/index.rst b/docs/source/index.rst index 9a317c924..f507a8c54 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -7,9 +7,10 @@ Welcome to OpenFPGA's documentation! ==================================== .. toctree:: - :caption: Motivation + :maxdepth: 2 + :caption: Overview - motivation + overview/index .. toctree:: :maxdepth: 2 diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index 1be9ec688..dfdb22e8e 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -5,6 +5,16 @@ Testbench In this part, we will introduce the hierarchy, dependency and functionality of each Verilog testbench, which are generated to verify a FPGA fabric implemented with an application. ++-----------------+---------+----------------+---------------+ +| Testbench Type | Runtime | Test Vector | Test Coverage | ++=================+=========+================+===============+ +| Full | Long | Random Stimuli | Full fabric | ++-----------------+---------+----------------+---------------+ +| Formal-oriented | Short | Random Stimuli | Programmable | +| | | or | fabric only | +| | | Formal Method | | ++-----------------+---------+----------------+---------------+ + OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented. Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a). To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. diff --git a/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst index 8ef7e3858..3ef6e9fb5 100644 --- a/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst +++ b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst @@ -11,8 +11,6 @@ To launch OpenFPGA shell, users can choose two modes. Launch OpenFPGA in interactive mode where users type-in command by command and get runtime results - .. warning:: Currently OpenFPGA does not support continued lines and comments - .. option:: --file or -f Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them diff --git a/docs/source/figures/OpenFPGA_logo.pdf b/docs/source/overview/figures/OpenFPGA_logo.pdf similarity index 100% rename from docs/source/figures/OpenFPGA_logo.pdf rename to docs/source/overview/figures/OpenFPGA_logo.pdf diff --git a/docs/source/figures/OpenFPGA_logo.png b/docs/source/overview/figures/OpenFPGA_logo.png similarity index 100% rename from docs/source/figures/OpenFPGA_logo.png rename to docs/source/overview/figures/OpenFPGA_logo.png diff --git a/docs/source/figures/fpga_sdc_motivation.png b/docs/source/overview/figures/fpga_sdc_motivation.png similarity index 100% rename from docs/source/figures/fpga_sdc_motivation.png rename to docs/source/overview/figures/fpga_sdc_motivation.png diff --git a/docs/source/figures/fpga_verilog_motivation.png b/docs/source/overview/figures/fpga_verilog_motivation.png similarity index 100% rename from docs/source/figures/fpga_verilog_motivation.png rename to docs/source/overview/figures/fpga_verilog_motivation.png diff --git a/docs/source/figures/openfpga_arch_lang_coverage.png b/docs/source/overview/figures/openfpga_arch_lang_coverage.png similarity index 100% rename from docs/source/figures/openfpga_arch_lang_coverage.png rename to docs/source/overview/figures/openfpga_arch_lang_coverage.png diff --git a/docs/source/figures/openfpga_flow.png b/docs/source/overview/figures/openfpga_flow.png similarity index 100% rename from docs/source/figures/openfpga_flow.png rename to docs/source/overview/figures/openfpga_flow.png diff --git a/docs/source/figures/openfpga_motivation.png b/docs/source/overview/figures/openfpga_motivation.png similarity index 100% rename from docs/source/figures/openfpga_motivation.png rename to docs/source/overview/figures/openfpga_motivation.png diff --git a/docs/source/overview/index.rst b/docs/source/overview/index.rst new file mode 100644 index 000000000..32b8fa75f --- /dev/null +++ b/docs/source/overview/index.rst @@ -0,0 +1,9 @@ +.. _overview: + Overview + +.. toctree:: + :maxdepth: 2 + + motivation + + tech_highlights diff --git a/docs/source/motivation.rst b/docs/source/overview/motivation.rst similarity index 100% rename from docs/source/motivation.rst rename to docs/source/overview/motivation.rst diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst new file mode 100644 index 000000000..8ec322b67 --- /dev/null +++ b/docs/source/overview/tech_highlights.rst @@ -0,0 +1,90 @@ +Technical Highlights +-------------------- + +The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**) + +Supported Circuit Designs +~~~~~~~~~~~~~~~~~~~~~~~~~ + ++---------------+-----------------+--------------+-------------------------+ +| Circuit Types | Auto-generation | User-Defined | Design Topologies | ++===============+=================+==============+=========================+ +| Inverter | Yes | Yes | - Power-gating | ++---------------+-----------------+--------------+-------------------------+ +| Buffer | Yes | Yes | - Tapered buffers | +| | | | - Power-gating | ++---------------+-----------------+--------------+-------------------------+ +| AND gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| OR gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| MUX2 gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| Pass gate | Yes | Yes | - Transmission gate | +| | | | - Pass transistor | ++---------------+-----------------+--------------+-------------------------+ +| Look-Up Table | Yes | Yes | - **Any size** | +| | | | - Single-output LUT | +| | | | - Fracturable LUT | +| | | | - Buffer location | ++---------------+-----------------+--------------+-------------------------+ +| Routing | Yes | No | - **Any size** | +| Multiplexer | | | - Buffer location | +| | | | - One-level structure | +| | | | - Treee structure | +| | | | - Multi-level structure | +| | | | - Local encoders | +| | | | - Constant inputs | ++---------------+-----------------+--------------+-------------------------+ +| Configurable | No | Yes | - Latch | +| Memory | | | - SRAM | +| | | | - D-type flip-flop | ++---------------+-----------------+--------------+-------------------------+ +| Block RAM | No | Yes | - Single-port | +| | | | - Dual-port | +| | | | - Fracturable | +| | | | - **Any size** | ++---------------+-----------------+--------------+-------------------------+ +| Arithmetic | No | Yes | - **Any size** | +| Units | | | - Multiplier | +| | | | - Adder | ++---------------+-----------------+--------------+-------------------------+ +| I/O | No | Yes | - General purpose I/O | +| | | | - Bi-directional buffer | +| | | | - AIB | ++---------------+-----------------+--------------+-------------------------+ + + +* The user defined netlist could come from a standard cell + +Supported FPGA Architectures +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +We support most FPGA architectures that VPR can support! +The following are most commonly seen architectural features: + ++--------------------+----------------------------------------------+ +| Block Type | Architecture features | ++====================+==============================================+ +| Programmable Block | - Single-mode Configurable Logic Block (CLB) | +| | - Multi-mode Configurable Logic Block (CLB) | +| | - Single-mode heterogeneous blocks | +| | - Multi-mode heterogeneous blocks | +| | - Flexible local routing architecture | ++--------------------+----------------------------------------------+ +| Routing Block | - Tileable routing architecture | +| | - Flexible connectivity | +| | - Flexible Switch Block Patterns | ++--------------------+----------------------------------------------+ + +Supported Verilog Modeling +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs + +- Synthesizable Behavioral Verilog + +- Structural Verilog + +- Implicit/Explicit port mapping + From c8339fc47393b3702ae0abbfd01710dd918a66a5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:00:30 -0600 Subject: [PATCH 144/330] [Documentation] Typo fix --- docs/source/overview/tech_highlights.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index 8ec322b67..f3b04b37a 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -31,7 +31,7 @@ Supported Circuit Designs | Routing | Yes | No | - **Any size** | | Multiplexer | | | - Buffer location | | | | | - One-level structure | -| | | | - Treee structure | +| | | | - Tree structure | | | | | - Multi-level structure | | | | | - Local encoders | | | | | - Constant inputs | From 56ab63d93915b2f48967de7ab634953ebc2dbd96 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:02:15 -0600 Subject: [PATCH 145/330] [Documentation] Fix format in table --- docs/source/manual/fpga_verilog/testbench.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index dfdb22e8e..db3ed8835 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -11,7 +11,7 @@ In this part, we will introduce the hierarchy, dependency and functionality of e | Full | Long | Random Stimuli | Full fabric | +-----------------+---------+----------------+---------------+ | Formal-oriented | Short | Random Stimuli | Programmable | -| | | or | fabric only | +| | | | fabric only | | | | Formal Method | | +-----------------+---------+----------------+---------------+ From 800931c8400dc5291899a0a7c0d4ae08bcd0466d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:16:15 -0600 Subject: [PATCH 146/330] [Documentation] Add configuration protocol to technical highlights --- docs/source/overview/tech_highlights.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index f3b04b37a..f4a915da6 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -76,6 +76,11 @@ The following are most commonly seen architectural features: | | - Flexible connectivity | | | - Flexible Switch Block Patterns | +--------------------+----------------------------------------------+ +| Configuration | - Chain-based organization | +| Protocol | - Frame-based organization | +| | - Memory bank organization | +| | - Flatten organization | ++--------------------+----------------------------------------------+ Supported Verilog Modeling ~~~~~~~~~~~~~~~~~~~~~~~~~~ From d68427e47bedffa273a2d80eb1569697318e8222 Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Mon, 5 Oct 2020 21:35:22 -0400 Subject: [PATCH 147/330] Fixed blif formatting bug --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a331d506d..355187e1a 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -622,7 +622,7 @@ def run_vpr(): args.top_module, args.top_module) cmd += r"| sed 's/$/./' | fold -s -w80 " - cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$/ /'" + cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$//'" cmd += " > %s.blif" % args.top_module os.system(cmd) if not args.fix_route_chan_width: From 00295a003fb824eac349e13adbde9bdff14527dc Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Mon, 5 Oct 2020 16:27:08 -0400 Subject: [PATCH 148/330] Docs: Updated note to enable VPR's GUI --- docs/source/tutorials/compile.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst index cab9ffdd2..fc9a25b13 100644 --- a/docs/source/tutorials/compile.rst +++ b/docs/source/tutorials/compile.rst @@ -23,6 +23,8 @@ In general, please follow the steps to compile .. note:: recommand to use ``make -j`` to accelerate the compilation +.. note:: VPR's GUI requires gtk-3, and can be enabled with ``cmake .. -DVPR_USE_EZGL=on`` + **Quick Compilation Verification** To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository From 33bbe0ec489805098101b10f713cc4d9e140f25f Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Tue, 6 Oct 2020 15:09:22 -0400 Subject: [PATCH 149/330] FLOW: fixed display flag --- openfpga_flow/scripts/run_fpga_flow.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 46b242a75..223b20190 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -596,7 +596,7 @@ def run_pro_blif_3arg(): def collect_files_for_vpr(): # Sanitize provided Benchmark option if len(args.benchmark_files) > 1: - logger.error("Expecting Single Benchmark BLif file.") + logger.error("Expecting Single Benchmark Blif file.") if not os.path.isfile(args.benchmark_files[0] or ""): clean_up_and_exit("Provided Blif file not found") shutil.copy(args.benchmark_files[0], args.top_module+".blif") @@ -721,6 +721,9 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): ] if not args.disp: command += ["--disp", "off"] + else: + command += ["--disp", "on"] + if route_only: command += ["--route"] # Power options From 721bcce37333c87d94a280d4d6548187ebb70e8e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 17:43:35 -0600 Subject: [PATCH 150/330] [Tool] Change analysis SDC file name to track netlist name --- openfpga/src/base/openfpga_naming.cpp | 10 ++++++++++ openfpga/src/base/openfpga_naming.h | 3 +++ openfpga/src/fpga_sdc/analysis_sdc_writer.cpp | 2 +- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index f743ef3f6..2e16058c0 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -1445,4 +1445,14 @@ std::string generate_const_value_module_output_port_name(const size_t& const_val return generate_const_value_module_name(const_val); } +/********************************************************************* + * Generate the analysis SDC file name + * The format is + * _ + ********************************************************************/ +std::string generate_analysis_sdc_file_name(const std::string& circuit_name, + const std::string& file_name_postfix) { + return circuit_name + "_" + file_name_postfix; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 3f374b8e5..a43fe8bb0 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -264,6 +264,9 @@ std::string generate_const_value_module_name(const size_t& const_val); std::string generate_const_value_module_output_port_name(const size_t& const_val); +std::string generate_analysis_sdc_file_name(const std::string& circuit_name, + const std::string& file_name_postfix); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp index a4730cae6..ae145110b 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp @@ -228,7 +228,7 @@ void print_analysis_sdc(const AnalysisSdcOption& option, const std::vector& global_ports, const bool& compact_routing_hierarchy) { /* Create the file name for Verilog netlist */ - std::string sdc_fname(option.sdc_dir() + std::string(SDC_ANALYSIS_FILE_NAME)); + std::string sdc_fname(option.sdc_dir() + generate_analysis_sdc_file_name(vpr_ctx.atom().nlist.netlist_name(), std::string(SDC_ANALYSIS_FILE_NAME))); std::string timer_message = std::string("Generating SDC for Timing/Power analysis on the mapped FPGA '") + sdc_fname From d0014878d52fcdceb23bc5d92a8b74b01e5f112e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 20:24:57 -0600 Subject: [PATCH 151/330] [Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes --- ...N4_lut_use_and_switch_40nm_cc_openfpga.xml | 231 ++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml new file mode 100644 index 000000000..fa1dab3d7 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 82e7b159ce62e4bd30c1cfe3315726f1776504bd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 20:26:41 -0600 Subject: [PATCH 152/330] [Regression test] Add test case for fracturable LUT using AND gate to switch modes --- .../frac_lut4_and_switch/config/task.conf | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf new file mode 100644 index 000000000..2ff8d23d1 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml + +[BENCHMARKS] +# +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif +# Modelsim is ok with this but icarus fails due to poor support on timing and looping +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +bench1_top = routing_test +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v + +bench2_top = and2_or2 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From b8c20959b61fe403cf2e4baa8f6449280b5625b8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 20:29:00 -0600 Subject: [PATCH 153/330] [Regression test] Add new test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 08278e98a..d96917bd3 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -16,6 +16,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mo echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs + echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs From ea3a1b785cbb7e13c21415b0805e760018f69f58 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 21:44:18 -0600 Subject: [PATCH 154/330] [Documentation] Fix the path to OpenFPGA logo in the README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 1965b9b47..26310fc4a 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Getting Started with OpenFPGA +# Getting Started with OpenFPGA [![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From ccaa697e5af59fd957b16fe49df2d2aff85a5a00 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Oct 2020 22:40:37 -0600 Subject: [PATCH 155/330] [Documentation] Add links to technical features to examples --- .../arch_lang/circuit_model_examples.rst | 226 ++++++++++++++++-- docs/source/overview/tech_highlights.rst | 133 ++++++----- 2 files changed, 268 insertions(+), 91 deletions(-) diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index e93d18e6a..fe582a13a 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -30,6 +30,8 @@ Template - ``f_per_stage=""`` Define the ratio of driving strength between the levels of a tapered inverter/buffer. Default value is 4. +.. _circuit_model_inverter_1x_example: + Inverter 1x Example ``````````````````` @@ -59,6 +61,8 @@ This example shows: - Size of 1 for the output strength - The tapered parameter is not declared and is ``false`` by default +.. _circuit_model_power_gated_inverter_example: + Power-gated Inverter 1x example ``````````````````````````````` @@ -74,7 +78,9 @@ The XML code describing an inverter which can be power-gated by the control sign -.. note:: For power-gated inverters: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated inverters are auto-generated , all the ``config_enable`` signals must be ``global`` signals as well. If the pwoer-gated inverters come from user-defined netlists, restrictions on ``global`` signals are free. +.. note:: For power-gated inverters: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated inverters are auto-generated, all the ``config_enable`` signals must be ``global`` signals as well. If the power-gated inverters come from user-defined netlists, restrictions on ``global`` signals are free. + +.. _circuit_model_buffer_2x_example: Buffer 2x example ````````````````` @@ -104,6 +110,26 @@ This example shows: - Size of 2 for the output strength - The tapered parameter is not declared and is ``false`` by default +.. _circuit_model_power_gated_buffer_example: + +Power-gated Buffer 4x example +````````````````````````````` + +The XML code describing a buffer which can be power-gated by the control signals ``EN`` and ``ENB`` : + +.. code-block:: xml + + + + + + + + + +.. note:: For power-gated buffers: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated buffers are auto-generated, all the ``config_enable`` signals must be ``global`` signals as well. If the power-gated buffers come from user-defined netlists, restrictions on ``global`` signals are free. + +.. _circuit_model_tapered_inv_16x_example: Tapered inverter 16x example ```````````````````````````` @@ -123,7 +149,7 @@ The XML code describing this inverter is: .. code-block:: xml - + @@ -133,7 +159,30 @@ This example shows: - The topology chosen as inverter - Size of 1 for the first stage output strength - The number of stage is set to 3 by - - f_per_stage is set to 4. Then 2nd stage output strength is 4* the 1st stage output strength (so 4*1 = 4) and the 3rd stage output strength is 4* the 2nd stage output strength (so 4*4 = 16). + - f_per_stage is set to 4. As a result, 2nd stage output strength is 4x, and the 3rd stage output strength is 16x. + +.. _circuit_model_tapered_buffer_64x_example: + +Tapered buffer 64x example +`````````````````````````` + +The XML code describing a 4-stage buffer is: + +.. code-block:: xml + + + + + + + + +This example shows: + - The topology chosen as buffer + - Size of 1 for the first stage output strength + - The number of stage is set to 4 by + - f_per_stage is set to 2. As a result, 2nd stage output strength is 4*, the 3rd stage output strength is 16*, and the 4th stage output strength is 64x. + Pass-gate Logic ~~~~~~~~~~~~~~~ @@ -163,6 +212,8 @@ Template .. note:: ``nmos_size`` and ``pmos_size`` are required for FPGA-SPICE +.. _circuit_model_tgate_example: + Transmission-gate Example ````````````````````````` @@ -192,6 +243,8 @@ This example shows: - A ``transmission_gate`` built with a *n*-type transistor in the size of 1 and a *p*-type transistor in the size of 2. - 3 inputs considered, 1 for datapath signal and 2 to turn on/off the transistors gates +.. _circuit_model_pass_transistor_example: + Pass-transistor Example ``````````````````````` @@ -240,6 +293,8 @@ Template .. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. +.. _circuit_model_sram_blwl_example: + SRAM with BL/WL ``````````````` .. _fig_sram_blwl: @@ -268,6 +323,8 @@ The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwl` .. note:: When the ``memory_bank`` type of configuration procotol is specified, SRAM modules should have a BL and a WL. +.. _circuit_model_config_latch_example: + Configurable Latch `````````````````` @@ -319,8 +376,37 @@ Template - ``topology="AND|OR|MUX2"`` Specify the logic functionality of a gate. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported. -2-input OR Gate Example -``````````````````````` +.. _circuit_model_and2_example: + +2-input AND Gate +```````````````` + +.. code-block:: xml + + + + + + + + + + 10e-12 8e-12 + + + 10e-12 7e-12 + + + +This example shows: + - A 2-input AND gate without any input and output buffers + - Propagation delay from input ``a`` to ``out`` is 10ps in rising edge and and 8ps in falling edge + - Propagation delay from input ``b`` to ``out`` is 10ps in rising edge and 7ps in falling edge + +.. _circuit_model_or2_example: + +2-input OR Gate +``````````````` .. code-block:: xml @@ -344,8 +430,10 @@ This example shows: - Propagation delay from input ``a`` to ``out`` is 10ps in rising edge and and 8ps in falling edge - Propagation delay from input ``b`` to ``out`` is 10ps in rising edge and 7ps in falling edge -MUX2 Gate Example -``````````````````````` +.. _circuit_model_mux2_gate_example: + +MUX2 Gate +````````` .. code-block:: xml @@ -409,7 +497,9 @@ Template .. note:: When multiplexers are not provided by users, the size of ports do not have to be consistent with actual numbers in the architecture. -One-level Mux Example +.. _circuit_model_mux_1level_example: + +One-level Multiplexer ````````````````````` :numref:`fig_mux1` illustrates an example of multiplexer modelling, which consists of input/output buffers and a transmission-gate-based tree structure. @@ -443,8 +533,10 @@ This example shows: - The multiplexer will be built by transmission gate using the circuit model ``tgate`` - The multiplexer will have 4 inputs and 4 SRAMs to control which datapath to propagate -Tree-like Multiplexer Example -````````````````````````````` +.. _circuit_model_mux_tree_example: + +Tree-like Multiplexer +````````````````````` :numref:`fig_mux` illustrates an example of multiplexer modelling, which consists of input/output buffers and a transmission-gate-based tree structure. @@ -477,8 +569,10 @@ This example shows: - The multiplexer will be built by transmission gate using the circuit model ``tgate`` - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate -Standard Cell Multiplexer Example -````````````````````````````````` +.. _circuit_model_mux_stdcell_example: + +Standard Cell Multiplexer +````````````````````````` .. code-block:: xml @@ -497,6 +591,74 @@ This example shows: - All the outputs will be buffered using the circuit model ``tapbuf4`` - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate +.. _circuit_model_mux_multilevel_example: + +Multi-level Multiplexer +``````````````````````` +.. code-block:: xml + + + + + + + + + + + +This example shows: + - A two-level 16-input CMOS multiplexer built by the transmission gate ``TGATE`` + - All the inputs will be buffered using the circuit model ``inv1x`` + - All the outputs will be buffered using the circuit model ``tapbuf4`` + - The multiplexer will have 16 inputs and 8 SRAMs to control which datapath to propagate + +.. _circuit_model_mux_local_encoder_example: + +Multiplexer with Local Encoder +`````````````````````````````` +.. code-block:: xml + + + + + + + + + + + +This example shows: + - A two-level 16-input CMOS multiplexer built by the transmission gate ``TGATE`` + - All the inputs will be buffered using the circuit model ``inv1x`` + - All the outputs will be buffered using the circuit model ``tapbuf4`` + - The multiplexer will have 16 inputs and 4 SRAMs to control which datapath to propagate + - Two local encoders are generated between the SRAMs and multiplexing structure to reduce the number of configurable memories required. + +.. _circuit_model_mux_const_input_example: + +Multiplexer with Constant Input +``````````````````````````````` +.. code-block:: xml + + + + + + + + + + + +This example shows: + - A two-level 16-input CMOS multiplexer built by the transmission gate ``TGATE`` + - All the inputs will be buffered using the circuit model ``inv1x`` + - All the outputs will be buffered using the circuit model ``tapbuf4`` + - The multiplexer will have 15 inputs and 8 SRAMs to control which datapath to propagate + - An constant input toggled at logic '1' is added in addition to the 14 regular inputs + Look-Up Tables ~~~~~~~~~~~~~~ @@ -576,8 +738,10 @@ Template .. note:: The size of a mode-selection SRAM port should be consistent to the number of '1s' or '0s' in the ``tri_state_map``. -Single-Output LUT Example -````````````````````````` +.. _circuit_model_single_output_lut_example: + +Single-Output LUT +````````````````` :numref:`fig_lut` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure. @@ -609,8 +773,10 @@ This example shows: - The multiplexer inside LUT will be built with transmission gate using circuuit model ``inv1x`` - There are no internal buffered inserted to any intermediate stage of a LUT -Fracturable LUT Example -````````````````````````` +.. _circuit_model_frac_lut_example: + +Fracturable LUT +``````````````` .. code-block:: xml @@ -672,8 +838,10 @@ Template .. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic. -Flip-Flop example -````````````````` +.. _circuit_model_dff_example: + +D-type Flip-Flop +```````````````` :numref:`fig_ff` illustrates an example of regular flip-flop. @@ -702,8 +870,10 @@ This example shows: - The flip-flop has ``set`` and ``reset`` functionalities - The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file -Configuration-chain Flip-flop Example -````````````````````````````````````` +.. _circuit_model_ccff_example: + +Configuration-chain Flip-flop +````````````````````````````` :numref:`fig_ccff` illustrates an example of scan-chain flop-flop used to build a configuration chain. @@ -756,8 +926,10 @@ Template .. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis. -1-bit Full Adder Example -```````````````````````` +.. _circuit_model_full_adder_example: + +Full Adder +`````````` .. code-block:: xml @@ -857,10 +1029,12 @@ Template .. note:: The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. -I/O Pad Example -``````````````` +.. _circuit_model_gpio_example: -:numref:`fig_iopad` depicts an I/O pad. +General Purpose I/O +``````````````````` + +:numref:`fig_iopad` depicts a general purpose I/O pad. .. _fig_iopad: @@ -870,7 +1044,7 @@ I/O Pad Example An example of an IO-Pad -The code describing this IO-Pad is: +The code describing this I/O-Pad is: .. code-block:: xml diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index f4a915da6..fa1a364e3 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -6,53 +6,56 @@ The follow lists of technical features are created to help users spot their need Supported Circuit Designs ~~~~~~~~~~~~~~~~~~~~~~~~~ -+---------------+-----------------+--------------+-------------------------+ -| Circuit Types | Auto-generation | User-Defined | Design Topologies | -+===============+=================+==============+=========================+ -| Inverter | Yes | Yes | - Power-gating | -+---------------+-----------------+--------------+-------------------------+ -| Buffer | Yes | Yes | - Tapered buffers | -| | | | - Power-gating | -+---------------+-----------------+--------------+-------------------------+ -| AND gate | Yes | Yes | - 2-input | -+---------------+-----------------+--------------+-------------------------+ -| OR gate | Yes | Yes | - 2-input | -+---------------+-----------------+--------------+-------------------------+ -| MUX2 gate | Yes | Yes | - 2-input | -+---------------+-----------------+--------------+-------------------------+ -| Pass gate | Yes | Yes | - Transmission gate | -| | | | - Pass transistor | -+---------------+-----------------+--------------+-------------------------+ -| Look-Up Table | Yes | Yes | - **Any size** | -| | | | - Single-output LUT | -| | | | - Fracturable LUT | -| | | | - Buffer location | -+---------------+-----------------+--------------+-------------------------+ -| Routing | Yes | No | - **Any size** | -| Multiplexer | | | - Buffer location | -| | | | - One-level structure | -| | | | - Tree structure | -| | | | - Multi-level structure | -| | | | - Local encoders | -| | | | - Constant inputs | -+---------------+-----------------+--------------+-------------------------+ -| Configurable | No | Yes | - Latch | -| Memory | | | - SRAM | -| | | | - D-type flip-flop | -+---------------+-----------------+--------------+-------------------------+ -| Block RAM | No | Yes | - Single-port | -| | | | - Dual-port | -| | | | - Fracturable | -| | | | - **Any size** | -+---------------+-----------------+--------------+-------------------------+ -| Arithmetic | No | Yes | - **Any size** | -| Units | | | - Multiplier | -| | | | - Adder | -+---------------+-----------------+--------------+-------------------------+ -| I/O | No | Yes | - General purpose I/O | -| | | | - Bi-directional buffer | -| | | | - AIB | -+---------------+-----------------+--------------+-------------------------+ ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Circuit Types | Auto-generation | User-Defined | Design Topologies | ++===============+=================+==============+=====================================================+ +| Inverter | Yes | Yes | - :ref:`circuit_model_power_gated_inverter_example` | +| | | | - :ref:`circuit_model_inverter_1x_example` | +| | | | - :ref:`circuit_model_tapered_inv_16x_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Buffer | Yes | Yes | - :ref:`circuit_model_buffer_2x_example` | +| | | | - :ref:`circuit_model_power_gated_buffer_example` | +| | | | - :ref:`circuit_model_tapered_buffer_64x_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| AND gate | Yes | Yes | - :ref:`circuit_model_and2_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| OR gate | Yes | Yes | - :ref:`circuit_model_or2_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| MUX2 gate | Yes | Yes | - :ref:`circuit_model_mux2_gate_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Pass gate | Yes | Yes | - :ref:`circuit_model_tgate_example` | +| | | | - :ref:`circuit_model_pass_transistor_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Look-Up Table | Yes | Yes | - **Any size** | +| | | | - :ref:`circuit_model_single_output_lut_example` | +| | | | - :ref:`circuit_model_frac_lut_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Routing | Yes | No | - **Any size** | +| Multiplexer | | | - :ref:`circuit_model_mux_multilevel_example` | +| | | | - :ref:`circuit_model_mux_1level_example` | +| | | | - :ref:`circuit_model_mux_tree_example` | +| | | | - :ref:`circuit_model_mux_stdcell_example` | +| | | | - :ref:`circuit_model_mux_local_encoder_example` | +| | | | - :ref:`circuit_model_mux_const_input_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` | +| Memory | | | - :ref:`circuit_model_sram_blwl_example` | +| | | | - :ref:`circuit_model_dff_example` | +| | | | - :ref:`circuit_model_ccff_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Block RAM | No | Yes | - **Any size** | +| | | | - Single-port | +| | | | - Dual-port | +| | | | - Fracturable | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| Arithmetic | No | Yes | - **Any size** | +| Units | | | - Multiplier | +| | | | - :ref:`circuit_model_full_adder_example` | ++---------------+-----------------+--------------+-----------------------------------------------------+ +| I/O | No | Yes | - :ref:`circuit_model_gpio_example` | +| | | | - Bi-directional buffer | +| | | | - AIB | ++---------------+-----------------+--------------+-----------------------------------------------------+ * The user defined netlist could come from a standard cell @@ -63,24 +66,24 @@ Supported FPGA Architectures We support most FPGA architectures that VPR can support! The following are most commonly seen architectural features: -+--------------------+----------------------------------------------+ -| Block Type | Architecture features | -+====================+==============================================+ -| Programmable Block | - Single-mode Configurable Logic Block (CLB) | -| | - Multi-mode Configurable Logic Block (CLB) | -| | - Single-mode heterogeneous blocks | -| | - Multi-mode heterogeneous blocks | -| | - Flexible local routing architecture | -+--------------------+----------------------------------------------+ -| Routing Block | - Tileable routing architecture | -| | - Flexible connectivity | -| | - Flexible Switch Block Patterns | -+--------------------+----------------------------------------------+ -| Configuration | - Chain-based organization | -| Protocol | - Frame-based organization | -| | - Memory bank organization | -| | - Flatten organization | -+--------------------+----------------------------------------------+ ++------------------------+----------------------------------------------+ +| Block Type | Architecture features | ++========================+==============================================+ +| Programmable Block | - Single-mode Configurable Logic Block (CLB) | +| | - Multi-mode Configurable Logic Block (CLB) | +| | - Single-mode heterogeneous blocks | +| | - Multi-mode heterogeneous blocks | +| | - Flexible local routing architecture | ++------------------------+----------------------------------------------+ +| Routing Block | - Tileable routing architecture | +| | - Flexible connectivity | +| | - Flexible Switch Block Patterns | ++------------------------+----------------------------------------------+ +| | - Chain-based organization | +| | - Frame-based organization | +| :ref:`config_protocol` | - Memory bank organization | +| | - Flatten organization | ++------------------------+----------------------------------------------+ Supported Verilog Modeling ~~~~~~~~~~~~~~~~~~~~~~~~~~ From 1ef0898f41adaeff8f762e34fe0a79cfebe1e4d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:31:51 -0600 Subject: [PATCH 156/330] [Tool] Now users can specify a different fabric netlist when generating Verilog testbench --- openfpga/src/base/openfpga_verilog.cpp | 2 ++ openfpga/src/base/openfpga_verilog_command.cpp | 4 ++++ openfpga/src/fpga_verilog/verilog_api.cpp | 1 + openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 8 +++++++- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h | 1 + openfpga/src/fpga_verilog/verilog_testbench_options.cpp | 9 +++++++++ openfpga/src/fpga_verilog/verilog_testbench_options.h | 6 ++++++ 7 files changed, 30 insertions(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 0c6367fc5..69c0b60d4 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -65,6 +65,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); + CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench"); CommandOptionId opt_fast_configuration = cmd.option("fast_configuration"); @@ -79,6 +80,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, */ VerilogTestbenchOption options; options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); + options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist)); options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench)); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 89c4e27e3..116d2842c 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -72,6 +72,10 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell Date: Mon, 12 Oct 2020 12:36:24 -0600 Subject: [PATCH 157/330] [Documentation] Update for new options in fpga-verilog --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 24dc3a603..667acb7c2 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -29,6 +29,8 @@ write_verilog_testbench - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists + - ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. + - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. From e510e79c1250c4e6ce60fd3fdd9dbf2f9b31d4de Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:42:43 -0600 Subject: [PATCH 158/330] [Flow] Add openfpga shell example script to use fabric netlist option --- ...tom_fabric_netlist_example_script.openfpga | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga new file mode 100644 index 000000000..f228d3c7a --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./TESTBENCH --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 9e1fd300dc062f442f44d503c458a77dbd88dfac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:47:58 -0600 Subject: [PATCH 159/330] [Test] Add test case for customized location of fabric netlists --- .../config/task.conf | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf new file mode 100644 index 000000000..943259966 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_fabric_netlist_file=./SRC/fabric_netlists.v + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 8941e3861363278c02c1282bf4e7cf0e63d8dcf1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:50:08 -0600 Subject: [PATCH 160/330] [Test] Enable verification in the new test case --- .../basic_tests/custom_fabric_netlist_location/config/task.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf index 943259966..bf54ec66a 100644 --- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -33,3 +33,4 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From e59377a3ec7b99e53a837e1c2834ccaeb080b018 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:52:01 -0600 Subject: [PATCH 161/330] [Flow] bug fix in the sample script for fabric netlist customization --- .../custom_fabric_netlist_example_script.openfpga | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga index f228d3c7a..577ed9ce4 100644 --- a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./TESTBENCH --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here From dc68c52d0a41c215e414ab6cc008676e17a95792 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:53:34 -0600 Subject: [PATCH 162/330] [Test] Now use a light architecture to speed up the test case runtime --- .../custom_fabric_netlist_location/config/task.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf index bf54ec66a..cd23bc3f7 100644 --- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -17,12 +17,12 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_fabric_netlist_file=./SRC/fabric_netlists.v +openfpga_fabric_netlist_file=./FABRIC_NETLIST/fabric_netlists.v [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif From 6b6c018945f765b246d60791b16370972d3949ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:54:51 -0600 Subject: [PATCH 163/330] [Test] Add the new test case to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 8f5961618..474667b84 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -63,6 +63,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --deb echo -e "Testing Verilog testbench generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs +echo -e "Testing separated Verilog fabric netlists and testbench locations"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs + echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs From 570b494df768d66ba1a004af4cdb1cc2f08faa13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:38:54 -0600 Subject: [PATCH 164/330] [Test] Add test case for using GND signal as constant input for routing multiplexers --- .../const_input_gnd/config/task.conf | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf new file mode 100644 index 000000000..4d743f8a9 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 99b1e68d923ce7ea62d475a8112c742a3c0a0e13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:39:27 -0600 Subject: [PATCH 165/330] [Architecture] Add architecture using GND as constant inputs for multiplexers --- ...N4_40nm_frame_const_input_gnd_openfpga.xml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml new file mode 100644 index 000000000..129b5e369 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From e5facf88662a2ae40a908ea81d35eed449082b52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:40:49 -0600 Subject: [PATCH 166/330] [Test] Deploy const gnd test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index d96917bd3..73a549bd1 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -70,6 +70,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_onl echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs From c5bcd934086b8c53169d78d847e906479ffae34a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:57:21 -0600 Subject: [PATCH 167/330] [Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input --- ..._N4_40nm_frame_no_const_input_openfpga.xml | 183 ++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml new file mode 100644 index 000000000..0f2c44d7a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml @@ -0,0 +1,183 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 97c3bf7ea0a6f72f6098a4ac34a66e5c5bb14f22 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:58:17 -0600 Subject: [PATCH 168/330] [Test] Add a test case for non-constant input multiplexers --- .../no_const_input/config/task.conf | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf new file mode 100644 index 000000000..64930a3a9 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 179ae355d012d2934821dd3c6663c8dd1c7e506a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 12:02:26 -0600 Subject: [PATCH 169/330] [Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops --- .../fpga_verilog/mux_design/no_const_input/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf index 64930a3a9..f463f0823 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf @@ -33,5 +33,5 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +#end_flow_with_test= #vpr_fpga_verilog_formal_verification_top_netlist= From 63f130d948c142101af8e2ef4e562d01dafd85b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 12:04:07 -0600 Subject: [PATCH 170/330] [Test] Deploy none constant input test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 73a549bd1..93b24e561 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -73,6 +73,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_on echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers without constant inputs"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs From 90e6021e434f77a8345cbc0f9298299b716391ca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 27 Oct 2020 09:53:57 -0600 Subject: [PATCH 171/330] [Doc] Update README with more links to documentation --- README.md | 50 ++++++++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/README.md b/README.md index 26310fc4a..ac7c8120e 100644 --- a/README.md +++ b/README.md @@ -6,36 +6,42 @@ The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. ## Compilation -Dependencies and help using docker can be found [**here**](./docs/source/tutorials/compile.rst). -**Compilation Steps:** -```bash -# Clone the repository and go inside it -git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA -mkdir build && cd build # Create a folder named build in the OpenPFGA repository -cmake .. # Create a Makefile in this folder using cmake -make # Compile the tool and its dependencies -``` -*cmake3.12 is recommended to compile OpenFPGA with GUI* +Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](./docs/source/tutorials/compile.rst). +It also includes detailed information about docker image. -**Quick Compilation Verification** -To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository. -```bash -python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs -``` +>**Compilation Steps:** +> +>```bash +># Clone the repository and go inside it +>git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA +>mkdir build && cd build # Create a folder named build in the OpenPFGA repository +>cmake .. # Create a Makefile in this folder using cmake +>make # Compile the tool and its dependencies +>``` -*Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.* +>**Quick Compilation Verification** +> +>To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository. +>```bash +>python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs +>``` +> +>*Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.* -**Supported Operating Systems** -We currently target OpenFPGA for: - 1. Ubuntu 18.04 - 2. Red Hat 7.5 - -*The tool was tested with these operating systems. It might work with earlier versions and other distributions.* +>**Supported Operating Systems** +> +>> We currently target OpenFPGA for: +> 1. Ubuntu 18.04 +> 2. Red Hat 7.5 +> +>*The tool was tested with these operating systems. It might work with earlier versions and other distributions.* ## Documentation + OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options. ## Tutorials + You can find some tutorials in the [**./tutorials**](./docs/source/tutorials/) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations. From 29431394a841d5b4b3ad2511c6ae75dda805c70f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 27 Oct 2020 10:08:25 -0600 Subject: [PATCH 172/330] [Doc] Add links to the technical summary in documentation for README --- README.md | 59 ++++++++++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/README.md b/README.md index ac7c8120e..56b4598d6 100644 --- a/README.md +++ b/README.md @@ -3,40 +3,49 @@ [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) ## Introduction + The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. +A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/tools.html). +We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights.html) before compiling. + ## Compilation -Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](./docs/source/tutorials/compile.rst). +Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/compile.html). It also includes detailed information about docker image. ->**Compilation Steps:** -> ->```bash -># Clone the repository and go inside it ->git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA ->mkdir build && cd build # Create a folder named build in the OpenPFGA repository ->cmake .. # Create a Makefile in this folder using cmake ->make # Compile the tool and its dependencies ->``` +--- ->**Quick Compilation Verification** -> ->To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository. ->```bash ->python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs ->``` -> ->*Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.* +**Compilation Steps:** +```bash +# Clone the repository and go inside it +git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA +mkdir build && cd build # Create a folder named build in the OpenPFGA repository +cmake .. # Create a Makefile in this folder using cmake +make # Compile the tool and its dependencies +``` ->**Supported Operating Systems** -> ->> We currently target OpenFPGA for: -> 1. Ubuntu 18.04 -> 2. Red Hat 7.5 -> ->*The tool was tested with these operating systems. It might work with earlier versions and other distributions.* +--- + +**Quick Compilation Verification** + +To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository. +```bash +python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs +``` + +*Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.* + +--- + +**Supported Operating Systems** + +We currently target OpenFPGA for: + 1. Ubuntu 18.04 + 2. Red Hat 7.5 + +*The tool was tested with these operating systems. It might work with earlier versions and other distributions.* ## Documentation From efb0162e3fed7c5e619dfbad4b1995ea2880856d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 28 Oct 2020 08:58:19 -0600 Subject: [PATCH 173/330] [Doc] Bug fix in tutorial due to renamed regression tests --- .../design_flow/verilog2verification.rst | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/docs/source/tutorials/design_flow/verilog2verification.rst b/docs/source/tutorials/design_flow/verilog2verification.rst index 505aa39c7..1455b729a 100644 --- a/docs/source/tutorials/design_flow/verilog2verification.rst +++ b/docs/source/tutorials/design_flow/verilog2verification.rst @@ -18,9 +18,9 @@ We will simply execute the following openfpga task-run by .. code-block:: shell - python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain + python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain -Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf``. +Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf``. .. note:: ``${OPENFPGA_PATH}`` is the root directory of OpenFPGA @@ -28,7 +28,7 @@ After this task-run, you can find all the generated netlists and testbenches at .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ .. note:: See :ref:`fabric_netlists` and :ref:`fpga_verilog_testbench` for the netlist details. @@ -43,7 +43,7 @@ The simulation results are logged in .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt If the verification passed, you should be able to see ``Simulation Succeed`` in the log file. @@ -53,7 +53,7 @@ To visualize the waveforms, you can use the `GTKWave .. code-block:: shell - gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & Manual Method ^^^^^^^^^^^^^ @@ -62,7 +62,7 @@ If you want to run iVerilog simulation manually, you can follow these steps: .. code-block:: shell - cd ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH + cd ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH source iverilog_output.txt @@ -75,7 +75,7 @@ If you want to apply full visibility to the signals, you need to change the foll .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v from @@ -94,19 +94,21 @@ Run Modelsim Simulation ~~~~~~~~~~~~~~~~~~~~~~~ Alternatively, you can run Modelsim simulations through openfpga_flow scripts or manually. +.. note:: Before starting, please ensure that Mentor Modelsim has been correctly installed on your local environment. + Through OpenFPGA Scripts ^^^^^^^^^^^^^^^^^^^^^^^^ You can simply call the python script in the following line: .. code-block:: shell - python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/full_testbench/configuration_chain --run_sim + python3 openfpga_flow/scripts/run_modelsim.py basic_tests/full_testbench/configuration_chain --run_sim The script will automatically create a Modelsim project at .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/ and run the simulation. @@ -131,7 +133,7 @@ Create a folder ``MSIM`` under .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/ Under the ``MSIM`` folder, create symbolic links to ``SRC`` folder and reference benchmarks by @@ -149,7 +151,7 @@ Add the following file to your project: .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v + ${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v Compile the netlists, create a simulation configuration and specify ``and2_autocheck_top_tb`` at the top unit. From 446f982410b0e7008e68144eb63abecf72a54477 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 28 Oct 2020 11:43:05 -0600 Subject: [PATCH 174/330] [Tool] Add warning when number of regions defined in fabric key is different than architecture --- openfpga/src/fabric/build_top_module.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 95d1c7dce..1da689cd2 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -402,6 +402,16 @@ int build_top_module(ModuleManager& module_manager, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(false == fabric_key.empty()); + /* Give a warning message that the fabric key may overwrite existing region organization. + * Only applicable when number of regions defined in configuration protocol is different + * than the number of regions defined in the fabric key + */ + if (size_t(config_protocol.num_regions()) != fabric_key.regions().size()) { + VTR_LOG_WARN("Fabric key will overwrite the region organization (='%ld') than architecture definition (=%d)!\n", + fabric_key.regions().size(), + config_protocol.num_regions()); + } + status = load_top_module_memory_modules_from_fabric_key(module_manager, top_module, fabric_key); if (CMD_EXEC_FATAL_ERROR == status) { From bd49ea95d42f6b38e68aabb71012ead1abea81f5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 28 Oct 2020 12:37:09 -0600 Subject: [PATCH 175/330] [Tool] Add function to comput configuration bits by region --- openfpga/src/fabric/build_top_module.cpp | 2 + .../src/fabric/build_top_module_memory.cpp | 62 +++++++++++++++++++ openfpga/src/fabric/build_top_module_memory.h | 7 +++ 3 files changed, 71 insertions(+) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 1da689cd2..9d6990286 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -438,6 +438,8 @@ int build_top_module(ModuleManager& module_manager, * we just need to find all the I/O ports from the child modules and build a list of it */ size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, config_protocol.type()); + vtr::vector top_module_num_config_bits = find_top_module_regional_num_config_bit(module_manager, top_module, circuit_lib, sram_model, config_protocol.type()); + if (0 < module_num_config_bits) { add_top_module_sram_ports(module_manager, top_module, circuit_lib, sram_model, diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index f8b1894ab..c4afe8b6e 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -590,6 +590,68 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Find the number of configuration bits in each region of + * the top-level module. + * + * Note: + * - This function should be called after the configurable children + * is loaded to the top-level module! + ********************************************************************/ +vtr::vector find_top_module_regional_num_config_bit(const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& config_protocol_type) { + /* Initialize the number of configuration bits for each region */ + vtr::vector num_config_bits(module_manager.regions(top_module).size(), 0); + + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + case CONFIG_MEM_SCAN_CHAIN: + case CONFIG_MEM_MEMORY_BANK: { + /* For flatten, chain and memory bank configuration protocol + * The number of configuration bits is the sum of configuration bits + * per configurable children in each region + */ + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + for (const ModuleId& child_module : module_manager.region_configurable_children(top_module, config_region)) { + num_config_bits[config_region] = find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type); + } + } + break; + } + case CONFIG_MEM_FRAME_BASED: { + /* For frame-based configuration protocol + * The number of configuration bits is the sum of + * - the maximum of configuration bits among configurable children + * - and the number of configurable children + */ + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + for (const ModuleId& child_module : module_manager.region_configurable_children(top_module, config_region)) { + size_t temp_num_config_bits = find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type); + num_config_bits[config_region] = std::max((int)temp_num_config_bits, (int)num_config_bits[config_region]); + } + + /* If there are more than 2 configurable children, we need a decoder + * Otherwise, we can just short wire the address port to the children + */ + if (1 < module_manager.region_configurable_children(top_module, config_region).size()) { + num_config_bits[config_region] += find_mux_local_decoder_addr_size(module_manager.region_configurable_children(top_module, config_region).size()); + } + } + + break; + } + + default: + VTR_LOG_ERROR("Invalid type of SRAM organization !\n"); + exit(1); + } + + return num_config_bits; +} + /******************************************************************** * Generate a list of ports that are used for SRAM configuration * to the top-level module diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index 87ca278cd..e82924783 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -7,6 +7,7 @@ #include #include +#include "vtr_vector.h" #include "vtr_ndmatrix.h" #include "module_manager.h" #include "circuit_types.h" @@ -45,6 +46,12 @@ int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager const ModuleId& top_module, const FabricKey& fabric_key); +vtr::vector find_top_module_regional_num_config_bit(const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& config_protocol_type); + void add_top_module_sram_ports(ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, From 448e88645a428e19da96b2ff5a8b22640e387478 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 12:42:03 -0600 Subject: [PATCH 176/330] [Tool] Support multiple memory banks in top-level module --- openfpga/src/fabric/build_top_module.cpp | 8 +- .../src/fabric/build_top_module_memory.cpp | 459 +++++++++++------- openfpga/src/fabric/build_top_module_memory.h | 4 +- .../fpga_bitstream/build_fabric_bitstream.cpp | 53 +- .../fpga_verilog/verilog_top_testbench.cpp | 93 +++- openfpga/src/utils/module_manager_utils.cpp | 21 +- openfpga/src/utils/module_manager_utils.h | 3 +- 7 files changed, 400 insertions(+), 241 deletions(-) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 9d6990286..a833929f2 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -437,13 +437,13 @@ int build_top_module(ModuleManager& module_manager, * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, config_protocol.type()); vtr::vector top_module_num_config_bits = find_top_module_regional_num_config_bit(module_manager, top_module, circuit_lib, sram_model, config_protocol.type()); - if (0 < module_num_config_bits) { + if (!top_module_num_config_bits.empty()) { add_top_module_sram_ports(module_manager, top_module, circuit_lib, sram_model, - config_protocol, module_num_config_bits); + config_protocol, + top_module_num_config_bits); } /* Add module nets to connect memory cells inside @@ -453,7 +453,7 @@ int build_top_module(ModuleManager& module_manager, add_top_module_nets_memory_config_bus(module_manager, decoder_lib, top_module, config_protocol, circuit_lib.design_tech_type(sram_model), - module_num_config_bits); + top_module_num_config_bits); } return status; diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index c4afe8b6e..913c99ed8 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -616,7 +616,7 @@ vtr::vector find_top_module_regional_num_config_bit(cons */ for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { for (const ModuleId& child_module : module_manager.region_configurable_children(top_module, config_region)) { - num_config_bits[config_region] = find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type); + num_config_bits[config_region] += find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type); } } break; @@ -671,10 +671,9 @@ size_t generate_top_module_sram_port_size(const ConfigProtocol& config_protocol, case CONFIG_MEM_STANDALONE: break; case CONFIG_MEM_SCAN_CHAIN: - /* CCFF head/tail are single-bit ports */ - sram_port_size = config_protocol.num_regions(); - break; case CONFIG_MEM_MEMORY_BANK: + /* CCFF head/tail, data input could be multi-bit ports */ + sram_port_size = config_protocol.num_regions(); break; case CONFIG_MEM_FRAME_BASED: break; @@ -715,9 +714,13 @@ void add_top_module_sram_ports(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const ConfigProtocol& config_protocol, - const size_t& num_config_bits) { + const vtr::vector& num_config_bits) { std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, config_protocol.type()); - size_t sram_port_size = generate_top_module_sram_port_size(config_protocol, num_config_bits); + size_t total_num_config_bits = 0; + for (const size_t& curr_num_config_bits : num_config_bits) { + total_num_config_bits += curr_num_config_bits; + } + size_t sram_port_size = generate_top_module_sram_port_size(config_protocol, total_num_config_bits); /* Add ports to the module manager */ switch (config_protocol.type()) { @@ -733,15 +736,24 @@ void add_top_module_sram_ports(ModuleManager& module_manager, BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1); module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT); - size_t bl_addr_size = find_memory_decoder_addr_size(num_config_bits); + /* BL address size is the largest among all the regions */ + size_t bl_addr_size = 0; + for (const ConfigRegionId& config_region : module_manager.regions(module_id)) { + bl_addr_size = std::max(bl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region])); + } BasicPort bl_addr_port(std::string(DECODER_BL_ADDRESS_PORT_NAME), bl_addr_size); module_manager.add_port(module_id, bl_addr_port, ModuleManager::MODULE_INPUT_PORT); - size_t wl_addr_size = find_memory_decoder_addr_size(num_config_bits); + /* WL address size is the largest among all the regions */ + size_t wl_addr_size = 0; + for (const ConfigRegionId& config_region : module_manager.regions(module_id)) { + wl_addr_size = std::max(wl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region])); + } BasicPort wl_addr_port(std::string(DECODER_WL_ADDRESS_PORT_NAME), wl_addr_size); module_manager.add_port(module_id, wl_addr_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1); + /* Data input should be dependent on the number of configuration regions*/ + BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), config_protocol.num_regions()); module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT); break; @@ -770,7 +782,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager, BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1); module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), num_config_bits); + BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), total_num_config_bits); module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1); @@ -787,11 +799,29 @@ void add_top_module_sram_ports(ModuleManager& module_manager, /********************************************************************* * Top-level function to add nets for memory banks - * - Find the number of BLs and WLs required + * Each configuration region has independent memory bank circuitry + * - Find the number of BLs and WLs required for each region * - Create BL and WL decoders, and add them to decoder library * - Create nets to connect from top-level module inputs to inputs of decoders * - Create nets to connect from outputs of decoders to BL/WL of configurable children * + * Detailed schematic of how memory banks are connected in the top-level: + * Consider a random Region X, local BL address lines are aligned to the LSB of the + * top-level BL address lines + * + * top_bl_addr[N-1:0] + * ^ + * | local_bl_addr[M-1:0], N > M + * | + * +-----+------------------+ + * | | | + * | +-------------------+ | + * | | Word Line Decoder | | + * | +-------------------+ | + * | | + * + * Detailed schematic of each memory bank: + * * WL_enable WL address * | | * v v @@ -834,7 +864,7 @@ static void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& top_module, - const size_t& num_config_bits) { + const vtr::vector& num_config_bits) { /* Find Enable port from the top-level module */ ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port_info = module_manager.module_port(top_module, en_port); @@ -843,6 +873,9 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag ModulePortId din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME)); BasicPort din_port_info = module_manager.module_port(top_module, din_port); + /* Data in port should match the number of configuration regions */ + VTR_ASSERT(din_port_info.get_width() == module_manager.regions(top_module).size()); + /* Find BL and WL address port from the top-level module */ ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME)); BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port); @@ -850,190 +883,240 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME)); BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port); - /* Find the number of BLs and WLs required to access each memory bit */ - size_t bl_addr_size = bl_addr_port_info.get_width(); - size_t wl_addr_size = wl_addr_port_info.get_width(); - size_t num_bls = find_memory_decoder_data_size(num_config_bits); - size_t num_wls = find_memory_decoder_data_size(num_config_bits); - - /* Add the BL decoder module - * Search the decoder library - * If we find one, we use the module. - * Otherwise, we create one and add it to the decoder library - */ - DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls, - true, true, false); - if (DecoderId::INVALID() == bl_decoder_id) { - bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false); - } - VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id); + /* Find the top-level number of BLs and WLs required to access each memory bit */ + size_t top_bl_addr_size = bl_addr_port_info.get_width(); + size_t top_wl_addr_size = wl_addr_port_info.get_width(); - /* Create a module if not existed yet */ - std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(bl_addr_size, num_bls); - ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name); - if (ModuleId::INVALID() == bl_decoder_module) { - /* BL decoder has the same ports as the frame-based decoders - * We reuse it here + /* Create separated memory bank circuitry, i.e., BL/WL decoders for each region */ + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + /* Find the number of BL/WLs and address sizes for the local decoders in the region */ + size_t num_bls = find_memory_decoder_data_size(num_config_bits[config_region]); + size_t num_wls = find_memory_decoder_data_size(num_config_bits[config_region]); + size_t local_bl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]); + size_t local_wl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]); + + VTR_ASSERT(top_bl_addr_size >= local_bl_addr_size); + VTR_ASSERT(top_wl_addr_size >= local_wl_addr_size); + + /************************************************************** + * Add the BL decoder module + * Search the decoder library + * If we find one, we use the module. + * Otherwise, we create one and add it to the decoder library */ - bl_decoder_module = build_bl_memory_decoder_module(module_manager, - decoder_lib, - bl_decoder_id); - } - VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module); - VTR_ASSERT(0 == module_manager.num_instance(top_module, bl_decoder_module)); - module_manager.add_child_module(top_module, bl_decoder_module); + DecoderId bl_decoder_id = decoder_lib.find_decoder(local_bl_addr_size, num_bls, + true, true, false); + if (DecoderId::INVALID() == bl_decoder_id) { + bl_decoder_id = decoder_lib.add_decoder(local_bl_addr_size, num_bls, true, true, false); + } + VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id); - /* Add the WL decoder module - * Search the decoder library - * If we find one, we use the module. - * Otherwise, we create one and add it to the decoder library - */ - DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls, - true, false, false); - if (DecoderId::INVALID() == wl_decoder_id) { - wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false); - } - VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id); + /* Create a module if not existed yet */ + std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(local_bl_addr_size, num_bls); + ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name); + if (ModuleId::INVALID() == bl_decoder_module) { + /* BL decoder has the same ports as the frame-based decoders + * We reuse it here + */ + bl_decoder_module = build_bl_memory_decoder_module(module_manager, + decoder_lib, + bl_decoder_id); + } + VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module); + size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module); + module_manager.add_child_module(top_module, bl_decoder_module); - /* Create a module if not existed yet */ - std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(wl_addr_size, num_wls); - ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name); - if (ModuleId::INVALID() == wl_decoder_module) { - /* BL decoder has the same ports as the frame-based decoders - * We reuse it here + /************************************************************** + * Add the WL decoder module + * Search the decoder library + * If we find one, we use the module. + * Otherwise, we create one and add it to the decoder library */ - wl_decoder_module = build_wl_memory_decoder_module(module_manager, - decoder_lib, - wl_decoder_id); - } - VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module); - VTR_ASSERT(0 == module_manager.num_instance(top_module, wl_decoder_module)); - module_manager.add_child_module(top_module, wl_decoder_module); - - /* Add module nets from the top module to BL decoder's inputs */ - ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port); - - ModulePortId bl_decoder_addr_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME)); - BasicPort bl_decoder_addr_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_addr_port); - - ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME)); - BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port); - - /* Top module Enable port -> BL Decoder Enable port */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, en_port, - bl_decoder_module, 0, bl_decoder_en_port); - - /* Top module Address port -> BL Decoder Address port */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, bl_addr_port, - bl_decoder_module, 0, bl_decoder_addr_port); - - /* Top module data_in port -> BL Decoder data_in port */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, din_port, - bl_decoder_module, 0, bl_decoder_din_port); - - /* Add module nets from the top module to WL decoder's inputs */ - ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME)); - BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port); - - ModulePortId wl_decoder_addr_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME)); - BasicPort wl_decoder_addr_port_info = module_manager.module_port(wl_decoder_module, bl_decoder_addr_port); - - /* Top module Enable port -> WL Decoder Enable port */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, en_port, - wl_decoder_module, 0, wl_decoder_en_port); - - /* Top module Address port -> WL Decoder Address port */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, wl_addr_port, - wl_decoder_module, 0, wl_decoder_addr_port); - - /* Add nets from BL data out to each configurable child */ - size_t cur_bl_index = 0; - - ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); - BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port); - - for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) { - ModuleId child_module = module_manager.configurable_children(top_module)[child_id]; - size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id]; - - /* Find the BL port */ - ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME)); - BasicPort child_bl_port_info = module_manager.module_port(child_module, child_bl_port); - - for (const size_t& sink_bl_pin : child_bl_port_info.pins()) { - /* Find the BL decoder data index: - * It should be the residual when divided by the number of BLs - */ - size_t bl_pin_id = std::floor(cur_bl_index / num_bls); - - /* Create net */ - ModuleNetId net = create_module_source_pin_net(module_manager, top_module, - bl_decoder_module, 0, - bl_decoder_dout_port, - bl_decoder_dout_port_info.pins()[bl_pin_id]); - VTR_ASSERT(ModuleNetId::INVALID() != net); - - /* Add net sink */ - module_manager.add_module_net_sink(top_module, net, - child_module, child_instance, child_bl_port, sink_bl_pin); - - /* Increment the BL index */ - cur_bl_index++; + DecoderId wl_decoder_id = decoder_lib.find_decoder(local_wl_addr_size, num_wls, + true, false, false); + if (DecoderId::INVALID() == wl_decoder_id) { + wl_decoder_id = decoder_lib.add_decoder(local_wl_addr_size, num_wls, true, false, false); } - } + VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id); - /* Add nets from WL data out to each configurable child */ - size_t cur_wl_index = 0; - - ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); - BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port); - - for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) { - ModuleId child_module = module_manager.configurable_children(top_module)[child_id]; - size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id]; - - /* Find the WL port */ - ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME)); - BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port); - - for (const size_t& sink_wl_pin : child_wl_port_info.pins()) { - /* Find the BL decoder data index: - * It should be the residual when divided by the number of BLs + /* Create a module if not existed yet */ + std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(local_wl_addr_size, num_wls); + ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name); + if (ModuleId::INVALID() == wl_decoder_module) { + /* BL decoder has the same ports as the frame-based decoders + * We reuse it here */ - size_t wl_pin_id = cur_wl_index % num_wls; - - /* Create net */ - ModuleNetId net = create_module_source_pin_net(module_manager, top_module, - wl_decoder_module, 0, - wl_decoder_dout_port, - wl_decoder_dout_port_info.pins()[wl_pin_id]); - VTR_ASSERT(ModuleNetId::INVALID() != net); - - /* Add net sink */ - module_manager.add_module_net_sink(top_module, net, - child_module, child_instance, child_wl_port, sink_wl_pin); - - /* Increment the WL index */ - cur_wl_index++; + wl_decoder_module = build_wl_memory_decoder_module(module_manager, + decoder_lib, + wl_decoder_id); } - } + VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module); + size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module); + module_manager.add_child_module(top_module, wl_decoder_module); - /* Add the BL and WL decoders to the end of configurable children list - * Note: this MUST be done after adding all the module nets to other regular configurable children - */ - module_manager.add_configurable_child(top_module, bl_decoder_module, 0); - module_manager.add_configurable_child(top_module, wl_decoder_module, 0); + /************************************************************** + * Add module nets from the top module to BL decoder's inputs + */ + ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME)); + BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port); + + ModulePortId bl_decoder_addr_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME)); + BasicPort bl_decoder_addr_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_addr_port); + + ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME)); + BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port); + + /* Data in port of the local BL decoder should always be 1 */ + VTR_ASSERT(1 == bl_decoder_din_port_info.get_width()); + + /* Top module Enable port -> BL Decoder Enable port */ + add_module_bus_nets(module_manager, + top_module, + top_module, 0, en_port, + bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_en_port); + + /* Top module Address port -> BL Decoder Address port */ + add_module_bus_nets(module_manager, + top_module, + top_module, 0, bl_addr_port, + bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_addr_port, + true); + + /* Top module data_in port -> BL Decoder data_in port: + * Note that each region has independent data_in connection from the top-level module + * The pin index is the configuration region index + */ + add_module_bus_nets(module_manager, + top_module, + top_module, 0, din_port, + bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port); + ModuleNetId din_net = create_module_source_pin_net(module_manager, top_module, + top_module, 0, + din_port, + din_port_info.pins()[size_t(config_region)]); + VTR_ASSERT(ModuleNetId::INVALID() != din_net); + + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, din_net, bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port, bl_decoder_din_port_info.pins()[0]); + + /************************************************************** + * Add module nets from the top module to WL decoder's inputs + */ + ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME)); + BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port); + + ModulePortId wl_decoder_addr_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME)); + BasicPort wl_decoder_addr_port_info = module_manager.module_port(wl_decoder_module, bl_decoder_addr_port); + + /* Top module Enable port -> WL Decoder Enable port */ + add_module_bus_nets(module_manager, + top_module, + top_module, 0, en_port, + wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_en_port); + + /* Top module Address port -> WL Decoder Address port */ + add_module_bus_nets(module_manager, + top_module, + top_module, 0, wl_addr_port, + wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_addr_port, + true); + + /************************************************************** + * Add nets from BL data out to each configurable child + */ + size_t cur_bl_index = 0; + + ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); + BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port); + + for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) { + ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; + + /* Find the BL port */ + ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME)); + BasicPort child_bl_port_info = module_manager.module_port(child_module, child_bl_port); + + for (const size_t& sink_bl_pin : child_bl_port_info.pins()) { + /* Find the BL decoder data index: + * It should be the residual when divided by the number of BLs + */ + size_t bl_pin_id = std::floor(cur_bl_index / num_bls); + if (!(bl_pin_id < bl_decoder_dout_port_info.pins().size())) + VTR_ASSERT(bl_pin_id < bl_decoder_dout_port_info.pins().size()); + + /* Create net */ + ModuleNetId net = create_module_source_pin_net(module_manager, top_module, + bl_decoder_module, curr_bl_decoder_instance_id, + bl_decoder_dout_port, + bl_decoder_dout_port_info.pins()[bl_pin_id]); + VTR_ASSERT(ModuleNetId::INVALID() != net); + + /* Add net sink */ + module_manager.add_module_net_sink(top_module, net, + child_module, child_instance, child_bl_port, sink_bl_pin); + + /* Increment the BL index */ + cur_bl_index++; + } + } + + /************************************************************** + * Add nets from WL data out to each configurable child + */ + size_t cur_wl_index = 0; + + ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); + BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port); + + for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) { + ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; + + /* Find the WL port */ + ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME)); + BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port); + + for (const size_t& sink_wl_pin : child_wl_port_info.pins()) { + /* Find the BL decoder data index: + * It should be the residual when divided by the number of BLs + */ + size_t wl_pin_id = cur_wl_index % num_wls; + + /* Create net */ + ModuleNetId net = create_module_source_pin_net(module_manager, top_module, + wl_decoder_module, curr_wl_decoder_instance_id, + wl_decoder_dout_port, + wl_decoder_dout_port_info.pins()[wl_pin_id]); + VTR_ASSERT(ModuleNetId::INVALID() != net); + + /* Add net sink */ + module_manager.add_module_net_sink(top_module, net, + child_module, child_instance, child_wl_port, sink_wl_pin); + + /* Increment the WL index */ + cur_wl_index++; + } + } + + /************************************************************** + * Add the BL and WL decoders to the end of configurable children list + * Note: this MUST be done after adding all the module nets to other regular configurable children + */ + module_manager.add_configurable_child(top_module, bl_decoder_module, curr_bl_decoder_instance_id); + module_manager.add_configurable_child_to_region(top_module, + config_region, + bl_decoder_module, + curr_bl_decoder_instance_id, + module_manager.configurable_children(top_module).size() - 1); + + module_manager.add_configurable_child(top_module, wl_decoder_module, curr_wl_decoder_instance_id); + module_manager.add_configurable_child_to_region(top_module, + config_region, + wl_decoder_module, + curr_wl_decoder_instance_id, + module_manager.configurable_children(top_module).size() - 1); + } } /******************************************************************** @@ -1203,7 +1286,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& parent_module, const ConfigProtocol& config_protocol, - const size_t& num_config_bits) { + const vtr::vector& num_config_bits) { switch (config_protocol.type()) { case CONFIG_MEM_STANDALONE: add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module, @@ -1265,7 +1348,7 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, const ConfigProtocol& config_protocol, const e_circuit_model_design_tech& mem_tech, - const size_t& num_config_bits) { + const vtr::vector& num_config_bits) { vtr::ScopedStartFinishTimer timer("Add module nets for configuration buses"); diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index e82924783..7e93ca85a 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -57,14 +57,14 @@ void add_top_module_sram_ports(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const ConfigProtocol& config_protocol, - const size_t& num_config_bits); + const vtr::vector& num_config_bits); void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const ModuleId& parent_module, const ConfigProtocol& config_protocol, const e_circuit_model_design_tech& mem_tech, - const size_t& num_config_bits); + const vtr::vector& num_config_bits); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index 4c05a5389..ef2b7a3c8 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -58,7 +58,6 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b /* Find the child block that matches the instance name! */ ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); /* We must have one valid block id! */ - if (true != bitstream_manager.valid_block_id(child_block)) VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); /* Go recursively */ @@ -79,7 +78,6 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b /* Find the child block that matches the instance name! */ ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); /* We must have one valid block id! */ - if (true != bitstream_manager.valid_block_id(child_block)) VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); /* Go recursively */ @@ -126,6 +124,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana const ModuleManager& module_manager, const ModuleId& top_module, const ModuleId& parent_module, + const ConfigRegionId& config_region, const size_t& bl_addr_size, const size_t& wl_addr_size, const size_t& num_bls, @@ -138,11 +137,16 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana * we dive to the next level first! */ if (0 < bitstream_manager.block_children(parent_block).size()) { - /* For top module, we will skip the two decoders at the end of the configurable children list */ + /* For top module: + * - Use regional configurable children + * - we will skip the two decoders at the end of the configurable children list + */ std::vector configurable_children = module_manager.configurable_children(parent_module); size_t num_configurable_children = configurable_children.size(); if (parent_module == top_module) { + configurable_children = module_manager.region_configurable_children(parent_module, config_region); + VTR_ASSERT(2 <= configurable_children.size()); num_configurable_children -= 2; } @@ -157,6 +161,10 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) { ModuleId child_module = configurable_children[child_id]; size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; + if (parent_module == top_module) { + child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; + } + /* Get the instance name and ensure it is not empty */ std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); @@ -169,6 +177,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana /* Go recursively */ rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block, module_manager, top_module, child_module, + config_region, bl_addr_size, wl_addr_size, num_bls, num_wls, cur_mem_index, @@ -451,30 +460,14 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc break; } case CONFIG_MEM_MEMORY_BANK: { - - size_t cur_mem_index = 0; - /* Find BL address port size */ + /* Find global BL address port size */ ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME)); BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port); - /* Find WL address port size */ + /* Find global WL address port size */ ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME)); BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port); - /* Find BL and WL decoders which are the last two configurable children*/ - std::vector configurable_children = module_manager.configurable_children(top_module); - VTR_ASSERT(2 <= configurable_children.size()); - ModuleId bl_decoder_module = configurable_children[configurable_children.size() - 2]; - VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 2]); - ModuleId wl_decoder_module = configurable_children[configurable_children.size() - 1]; - VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 1]); - - ModulePortId bl_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); - BasicPort bl_port_info = module_manager.module_port(bl_decoder_module, bl_port); - - ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); - BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port); - /* Reserve bits before build-up */ fabric_bitstream.set_use_address(true); fabric_bitstream.set_use_wl_address(true); @@ -482,13 +475,27 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc fabric_bitstream.set_wl_address_length(wl_addr_port_info.get_width()); fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); - /* TODO: Currently only support 1 region. Will expand later! */ - VTR_ASSERT(1 == module_manager.regions(top_module).size()); + size_t cur_mem_index = 0; + /* Build bitstreams by region */ for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + /* Find port information for local BL and WL decoder in this region */ + std::vector configurable_children = module_manager.region_configurable_children(top_module, config_region); + VTR_ASSERT(2 <= configurable_children.size()); + ModuleId bl_decoder_module = configurable_children[configurable_children.size() - 2]; + ModuleId wl_decoder_module = configurable_children[configurable_children.size() - 1]; + + ModulePortId bl_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); + BasicPort bl_port_info = module_manager.module_port(bl_decoder_module, bl_port); + + ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); + BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port); + + /* Build the bitstream for all the blocks in this region */ FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block, module_manager, top_module, top_module, + config_region, bl_addr_port_info.get_width(), wl_addr_port_info.get_width(), bl_port_info.get_width(), diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index a5a6e1f82..b6da8f813 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1517,6 +1517,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, fp << ";"; fp << std::endl; + fp << "\t\t"; fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values); fp << ";"; fp << std::endl; @@ -1528,37 +1529,87 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, fp << std::endl; - /* Attention: the configuration chain protcol requires the last configuration bit is fed first - * We will visit the fabric bitstream in a reverse way + /* Reorganize the fabric bitstream by the same address across regions: + * This is due to that the length of fabric bitstream could be different in each region. + * Template: + * + * An example: + * 000000 00000 1011 + * + * Note: the std::map may cause large memory footprint for large bitstream databases! */ - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - /* When fast configuration is enabled, we skip zero data_in values */ - if ((true == fast_configuration) - && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { - continue; + std::map, std::vector> fabric_bits_by_addr; + for (const FabricBitRegionId& region : fabric_bitstream.regions()) { + for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { + /* Create string for BL address */ + VTR_ASSERT(bl_addr_port.get_width() == fabric_bitstream.bit_bl_address(bit_id).size()); + std::string bl_addr_str; + for (const char& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) { + bl_addr_str.push_back(addr_bit); + } + + /* Create string for WL address */ + VTR_ASSERT(wl_addr_port.get_width() == fabric_bitstream.bit_wl_address(bit_id).size()); + std::string wl_addr_str; + for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) { + wl_addr_str.push_back(addr_bit); + } + + /* Place the config bit */ + auto result = fabric_bits_by_addr.find(std::make_pair(bl_addr_str, wl_addr_str)); + if (result == fabric_bits_by_addr.end()) { + /* This is a new bit, resize the vector to the number of regions + * and deposit '0' to all the bits + */ + fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)] = std::vector(fabric_bitstream.regions().size(), false); + fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)][size_t(region)] = fabric_bitstream.bit_din(bit_id); + } else { + VTR_ASSERT_SAFE(result != fabric_bits_by_addr.end()); + result->second[size_t(region)] = fabric_bitstream.bit_din(bit_id); + } + } + } + + for (const auto& addr_din_pair : fabric_bits_by_addr) { + /* When fast configuration is enabled, + * the rule to skip any configuration bit should consider the whole data input values. + * Only all the bits in the din port match the value to be skipped, + * the programming cycle can be skipped! + */ + if (true == fast_configuration) { + bool skip_curr_bits = true; + for (const bool& bit : addr_din_pair.second) { + if (bit_value_to_skip != bit) { + skip_curr_bits = false; + break; + } + } + + if (true == skip_curr_bits) { + continue; + } } fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); fp << "(" << bl_addr_port.get_width() << "'b"; - VTR_ASSERT(bl_addr_port.get_width() == fabric_bitstream.bit_bl_address(bit_id).size()); - for (const char& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) { - fp << addr_bit; - } + VTR_ASSERT(bl_addr_port.get_width() == addr_din_pair.first.first.length()); + fp << addr_din_pair.first.first; fp << ", "; fp << wl_addr_port.get_width() << "'b"; - VTR_ASSERT(wl_addr_port.get_width() == fabric_bitstream.bit_wl_address(bit_id).size()); - for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) { - fp << addr_bit; - } + VTR_ASSERT(wl_addr_port.get_width() == addr_din_pair.first.second.length()); + fp << addr_din_pair.first.second; fp << ", "; - fp <<"1'b"; - if (true == fabric_bitstream.bit_din(bit_id)) { - fp << "1"; - } else { - VTR_ASSERT(false == fabric_bitstream.bit_din(bit_id)); - fp << "0"; + fp << din_port.get_width() << "'b"; + VTR_ASSERT(din_port.get_width() == addr_din_pair.second.size()); + for (const bool& din_value : addr_din_pair.second) { + if (true == din_value) { + fp << "1"; + } else { + VTR_ASSERT(false == din_value); + fp << "0"; + } } fp << ");" << std::endl; } diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 929897721..4117735a9 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -1793,6 +1793,16 @@ ModuleNetId create_module_source_pin_net(ModuleManager& module_manager, * - des_module should be the cur_module or a child of it * - src_instance should be valid and des_instance should be valid as well * - src port size should match the des port size + * + * Power options: + * - align_to_lsb: This is by default turned off! + * When enabled, the source and destination ports + * will be connected pin-by-pin starting from + * the Least Significant Bit (LSB) + * The source and destination ports are not required + * to be same in sizes. + * BE CAREFUL! This may cause dangling pins! + * Use when you know what you are doing! *******************************************************************/ void add_module_bus_nets(ModuleManager& module_manager, const ModuleId& cur_module_id, @@ -1801,7 +1811,8 @@ void add_module_bus_nets(ModuleManager& module_manager, const ModulePortId& src_module_port_id, const ModuleId& des_module_id, const size_t& des_instance_id, - const ModulePortId& des_module_port_id) { + const ModulePortId& des_module_port_id, + const bool& align_to_lsb) { VTR_ASSERT(true == module_manager.valid_module_id(cur_module_id)); VTR_ASSERT(true == module_manager.valid_module_id(src_module_id)); @@ -1825,7 +1836,8 @@ void add_module_bus_nets(ModuleManager& module_manager, const BasicPort& src_port = module_manager.module_port(src_module_id, src_module_port_id); const BasicPort& des_port = module_manager.module_port(des_module_id, des_module_port_id); - if (src_port.get_width() != des_port.get_width()) { + if ( (false == align_to_lsb) + && (src_port.get_width() != des_port.get_width())) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Unmatched port size: src_port %s is %lu while des_port %s is %lu!\n", src_port.get_name().c_str(), @@ -1837,6 +1849,11 @@ void add_module_bus_nets(ModuleManager& module_manager, /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { + /* Create net only when des_port has a valid pin! */ + if (pin_id >= des_port.pins().size()) { + continue; + } + ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]); diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index 28913e673..6cdf27fe8 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -165,7 +165,8 @@ void add_module_bus_nets(ModuleManager& module_manager, const ModulePortId& src_module_port_id, const ModuleId& des_module_id, const size_t& des_instance_id, - const ModulePortId& des_module_port_id); + const ModulePortId& des_module_port_id, + const bool& align_to_lsb = false); } /* end namespace openfpga */ From 75344744238f2e9266481df7ea547fb7d407b2fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 13:54:51 -0600 Subject: [PATCH 177/330] [Arch] Add architecture for multiple-region memory banks --- .../k4_N4_40nm_multi_region_bank_openfpga.xml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml new file mode 100644 index 000000000..3c074876d --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From ff386001c4f271886b53eff390c85c540221d938 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 13:56:32 -0600 Subject: [PATCH 178/330] [Test] Add openfpga task for multi-region memory banks --- .../multi_region_memory_bank/config/task.conf | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf new file mode 100644 index 000000000..a78899a35 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 987eccf586aa6b746cca7743b8dfaae3c459b6be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 16:26:45 -0600 Subject: [PATCH 179/330] [Tool] Bug fix in multi-region memory bank; Basic test passed --- .../src/fabric/build_top_module_memory.cpp | 74 +++++++----- .../fpga_bitstream/build_device_bitstream.cpp | 70 ++++++++---- .../fpga_bitstream/build_fabric_bitstream.cpp | 106 ++++++++++++------ .../fpga_verilog/verilog_module_writer.cpp | 2 +- openfpga/src/utils/module_manager_utils.cpp | 20 +--- openfpga/src/utils/module_manager_utils.h | 3 +- 6 files changed, 172 insertions(+), 103 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 913c99ed8..48eace3bd 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -811,7 +811,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager, * * top_bl_addr[N-1:0] * ^ - * | local_bl_addr[M-1:0], N > M + * | local_bl_addr[N-1:0] * | * +-----+------------------+ * | | | @@ -820,6 +820,32 @@ void add_top_module_sram_ports(ModuleManager& module_manager, * | +-------------------+ | * | | * + * The BL/WL decoders should have the same circuit designs no matter what region + * they are placed even when the number of configuration bits are different + * from one region to another! + * This is designed to avoid any address collision between memory banks + * since they are programmed in the same clock cycle + * For example: + * - Memory Bank A has 36 memory cells. + * Its BL decoder has 3 address bit and 6 data output bit + * Its WL decoder has 3 address bit and 6 data output bit + * - Memory Bank B has 16 memory cells. + * Its BL decoder has 2 address bit and 4 data output bit + * Its WL decoder has 2 address bit and 4 data output bit + * - If we try to program the 36th memory cell in bank A + * the BL address will be 3'b110 + * the WL address will be 3'b110 + * the data input will be 1'b0 + * - If we try to program the 4th memory cell in bank A + * the BL address will be 3'b010 + * the WL address will be 3'b010 + * the data input will be 1'b1 + * However, in both cases, this will trigger a parasitic programming in bank B + * the BL address will be 2'b10 + * the WL address will be 2'b10 + * Assume the data input is expected to be 1'b1 for bank B + * but it will be overwritten to 1'b0 when programming the 36th cell in bank A! + * * Detailed schematic of each memory bank: * * WL_enable WL address @@ -884,35 +910,37 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port); /* Find the top-level number of BLs and WLs required to access each memory bit */ - size_t top_bl_addr_size = bl_addr_port_info.get_width(); - size_t top_wl_addr_size = wl_addr_port_info.get_width(); + size_t bl_addr_size = bl_addr_port_info.get_width(); + size_t wl_addr_size = wl_addr_port_info.get_width(); + + /* Each memory bank has a unified number of BL/WLs */ + size_t num_bls = 0; + for (const size_t& curr_config_bits : num_config_bits) { + num_bls = std::max(num_bls, find_memory_decoder_data_size(curr_config_bits)); + } + + size_t num_wls = 0; + for (const size_t& curr_config_bits : num_config_bits) { + num_wls = std::max(num_wls, find_memory_decoder_data_size(curr_config_bits)); + } /* Create separated memory bank circuitry, i.e., BL/WL decoders for each region */ for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { - /* Find the number of BL/WLs and address sizes for the local decoders in the region */ - size_t num_bls = find_memory_decoder_data_size(num_config_bits[config_region]); - size_t num_wls = find_memory_decoder_data_size(num_config_bits[config_region]); - size_t local_bl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]); - size_t local_wl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]); - - VTR_ASSERT(top_bl_addr_size >= local_bl_addr_size); - VTR_ASSERT(top_wl_addr_size >= local_wl_addr_size); - /************************************************************** * Add the BL decoder module * Search the decoder library * If we find one, we use the module. * Otherwise, we create one and add it to the decoder library */ - DecoderId bl_decoder_id = decoder_lib.find_decoder(local_bl_addr_size, num_bls, + DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls, true, true, false); if (DecoderId::INVALID() == bl_decoder_id) { - bl_decoder_id = decoder_lib.add_decoder(local_bl_addr_size, num_bls, true, true, false); + bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false); } VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id); /* Create a module if not existed yet */ - std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(local_bl_addr_size, num_bls); + std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(bl_addr_size, num_bls); ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name); if (ModuleId::INVALID() == bl_decoder_module) { /* BL decoder has the same ports as the frame-based decoders @@ -932,15 +960,15 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag * If we find one, we use the module. * Otherwise, we create one and add it to the decoder library */ - DecoderId wl_decoder_id = decoder_lib.find_decoder(local_wl_addr_size, num_wls, + DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls, true, false, false); if (DecoderId::INVALID() == wl_decoder_id) { - wl_decoder_id = decoder_lib.add_decoder(local_wl_addr_size, num_wls, true, false, false); + wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false); } VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id); /* Create a module if not existed yet */ - std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(local_wl_addr_size, num_wls); + std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(wl_addr_size, num_wls); ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name); if (ModuleId::INVALID() == wl_decoder_module) { /* BL decoder has the same ports as the frame-based decoders @@ -979,17 +1007,12 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag add_module_bus_nets(module_manager, top_module, top_module, 0, bl_addr_port, - bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_addr_port, - true); + bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_addr_port); /* Top module data_in port -> BL Decoder data_in port: * Note that each region has independent data_in connection from the top-level module * The pin index is the configuration region index */ - add_module_bus_nets(module_manager, - top_module, - top_module, 0, din_port, - bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port); ModuleNetId din_net = create_module_source_pin_net(module_manager, top_module, top_module, 0, din_port, @@ -1018,8 +1041,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag add_module_bus_nets(module_manager, top_module, top_module, 0, wl_addr_port, - wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_addr_port, - true); + wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_addr_port); /************************************************************** * Add nets from BL data out to each configurable child diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index a2aa97f57..9229cce5f 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -62,37 +62,68 @@ size_t rec_estimate_device_bitstream_num_blocks(const ModuleManager& module_mana static size_t rec_estimate_device_bitstream_num_bits(const ModuleManager& module_manager, const ModuleId& top_module, + const ModuleId& parent_module, const e_config_protocol_type& config_protocol_type) { size_t num_bits = 0; /* If a child module has no configurable children, this is a leaf node * We can count it in. Otherwise, we should go recursively. */ - if (0 == module_manager.configurable_children(top_module).size()) { + if (0 == module_manager.configurable_children(parent_module).size()) { return 1; } - size_t num_configurable_children = module_manager.configurable_children(top_module).size(); - /* Frame-based configuration protocol will have 1 decoder - * if there are more than 1 configurable children + /* Two cases to walk through configurable children: + * - For top-level module: + * Iterate over the multiple regions and visit each configuration child under any region + * In each region, frame-based configuration protocol or memory bank protocol will contain + * decoders. We should bypass them when count the bitstream size + * - For other modules: + * Iterate over the configurable children regardless of regions */ - if ( (CONFIG_MEM_FRAME_BASED == config_protocol_type) - && (2 <= num_configurable_children)) { - num_configurable_children--; - } + if (parent_module == top_module) { + for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + size_t curr_region_num_config_child = module_manager.region_configurable_children(parent_module, config_region).size(); - /* Memory configuration protocol will have 2 decoders - * at the top-level - */ - if (CONFIG_MEM_MEMORY_BANK == config_protocol_type) { - std::string top_block_name = generate_fpga_top_module_name(); - if (top_module == module_manager.find_module(top_block_name)) { - num_configurable_children -= 2; + /* Frame-based configuration protocol will have 1 decoder + * if there are more than 1 configurable children + */ + if ( (CONFIG_MEM_FRAME_BASED == config_protocol_type) + && (2 <= curr_region_num_config_child)) { + curr_region_num_config_child--; + } + + /* Memory configuration protocol will have 2 decoders + * at the top-level + */ + if (CONFIG_MEM_MEMORY_BANK == config_protocol_type) { + VTR_ASSERT(2 <= curr_region_num_config_child); + curr_region_num_config_child -= 2; + } + + /* Visit all the children in a recursively way */ + for (size_t ichild = 0; ichild < curr_region_num_config_child; ++ichild) { + ModuleId child_module = module_manager.region_configurable_children(parent_module, config_region)[ichild]; + num_bits += rec_estimate_device_bitstream_num_bits(module_manager, top_module, child_module, config_protocol_type); + } + } + } else { + VTR_ASSERT_SAFE(parent_module == top_module); + + size_t num_configurable_children = module_manager.configurable_children(parent_module).size(); + + /* Frame-based configuration protocol will have 1 decoder + * if there are more than 1 configurable children + */ + if ( (CONFIG_MEM_FRAME_BASED == config_protocol_type) + && (2 <= num_configurable_children)) { + num_configurable_children--; + } + + for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { + ModuleId child_module = module_manager.configurable_children(parent_module)[ichild]; + num_bits += rec_estimate_device_bitstream_num_bits(module_manager, top_module, child_module, config_protocol_type); } - } - for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { - ModuleId child_module = module_manager.configurable_children(top_module)[ichild]; - num_bits += rec_estimate_device_bitstream_num_bits(module_manager, child_module, config_protocol_type); } return num_bits; @@ -141,6 +172,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, /* Estimate the number of bits to be added to the database */ size_t num_bits_to_reserve = rec_estimate_device_bitstream_num_bits(openfpga_ctx.module_graph(), + top_module, top_module, openfpga_ctx.arch().config_protocol.type()); bitstream_manager.reserve_bits(num_bits_to_reserve); diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index ef2b7a3c8..04d7fe714 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -141,48 +141,80 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana * - Use regional configurable children * - we will skip the two decoders at the end of the configurable children list */ - std::vector configurable_children = module_manager.configurable_children(parent_module); - - size_t num_configurable_children = configurable_children.size(); if (parent_module == top_module) { - configurable_children = module_manager.region_configurable_children(parent_module, config_region); + std::vector configurable_children = module_manager.region_configurable_children(parent_module, config_region); VTR_ASSERT(2 <= configurable_children.size()); - num_configurable_children -= 2; - } + size_t num_configurable_children = configurable_children.size() - 2; - /* Early exit if there is no configurable children */ - if (0 == num_configurable_children) { - /* Ensure that there should be no configuration bits in the parent block */ - VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); - return; - } - - for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) { - ModuleId child_module = configurable_children[child_id]; - size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; - if (parent_module == top_module) { - child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; + /* Early exit if there is no configurable children */ + if (0 == num_configurable_children) { + /* Ensure that there should be no configuration bits in the parent block */ + VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); + return; } - /* Get the instance name and ensure it is not empty */ - std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); - - /* Find the child block that matches the instance name! */ - ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); - /* We must have one valid block id! */ - if (true != bitstream_manager.valid_block_id(child_block)) - VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) { + ModuleId child_module = configurable_children[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; - /* Go recursively */ - rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block, - module_manager, top_module, child_module, - config_region, - bl_addr_size, wl_addr_size, - num_bls, num_wls, - cur_mem_index, - fabric_bitstream, - fabric_bitstream_region); + /* Get the instance name and ensure it is not empty */ + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + + /* Find the child block that matches the instance name! */ + ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); + /* We must have one valid block id! */ + VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + + /* Go recursively */ + rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block, + module_manager, top_module, child_module, + config_region, + bl_addr_size, wl_addr_size, + num_bls, num_wls, + cur_mem_index, + fabric_bitstream, + fabric_bitstream_region); + } + } else { + VTR_ASSERT(parent_module != top_module); + /* For other modules: + * - Use configurable children directly + * - no need to exclude decoders as they are not there + */ + std::vector configurable_children = module_manager.configurable_children(parent_module); + + size_t num_configurable_children = configurable_children.size(); + + /* Early exit if there is no configurable children */ + if (0 == num_configurable_children) { + /* Ensure that there should be no configuration bits in the parent block */ + VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); + return; + } + + for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) { + ModuleId child_module = configurable_children[child_id]; + size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; + + /* Get the instance name and ensure it is not empty */ + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + + /* Find the child block that matches the instance name! */ + ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); + /* We must have one valid block id! */ + VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + + /* Go recursively */ + rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block, + module_manager, top_module, child_module, + config_region, + bl_addr_size, wl_addr_size, + num_bls, num_wls, + cur_mem_index, + fabric_bitstream, + fabric_bitstream_region); + } } /* Ensure that there should be no configuration bits in the parent block */ VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); @@ -475,10 +507,10 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc fabric_bitstream.set_wl_address_length(wl_addr_port_info.get_width()); fabric_bitstream.reserve_bits(bitstream_manager.num_bits()); - size_t cur_mem_index = 0; - /* Build bitstreams by region */ for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { + size_t cur_mem_index = 0; + /* Find port information for local BL and WL decoder in this region */ std::vector configurable_children = module_manager.region_configurable_children(top_module, config_region); VTR_ASSERT(2 <= configurable_children.size()); diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 7d6883236..08e1b3adb 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -40,7 +40,7 @@ std::string generate_verilog_undriven_local_wire_name(const ModuleManager& modul if (!module_manager.instance_name(parent, child, instance_id).empty()) { wire_name = module_manager.instance_name(parent, child, instance_id); } else { - wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); + wire_name = module_manager.module_name(child) + std::string("_") + std::to_string(instance_id); wire_name += std::string("_"); } diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 4117735a9..7d56430b6 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -1794,15 +1794,6 @@ ModuleNetId create_module_source_pin_net(ModuleManager& module_manager, * - src_instance should be valid and des_instance should be valid as well * - src port size should match the des port size * - * Power options: - * - align_to_lsb: This is by default turned off! - * When enabled, the source and destination ports - * will be connected pin-by-pin starting from - * the Least Significant Bit (LSB) - * The source and destination ports are not required - * to be same in sizes. - * BE CAREFUL! This may cause dangling pins! - * Use when you know what you are doing! *******************************************************************/ void add_module_bus_nets(ModuleManager& module_manager, const ModuleId& cur_module_id, @@ -1811,8 +1802,7 @@ void add_module_bus_nets(ModuleManager& module_manager, const ModulePortId& src_module_port_id, const ModuleId& des_module_id, const size_t& des_instance_id, - const ModulePortId& des_module_port_id, - const bool& align_to_lsb) { + const ModulePortId& des_module_port_id) { VTR_ASSERT(true == module_manager.valid_module_id(cur_module_id)); VTR_ASSERT(true == module_manager.valid_module_id(src_module_id)); @@ -1836,8 +1826,7 @@ void add_module_bus_nets(ModuleManager& module_manager, const BasicPort& src_port = module_manager.module_port(src_module_id, src_module_port_id); const BasicPort& des_port = module_manager.module_port(des_module_id, des_module_port_id); - if ( (false == align_to_lsb) - && (src_port.get_width() != des_port.get_width())) { + if (src_port.get_width() != des_port.get_width()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Unmatched port size: src_port %s is %lu while des_port %s is %lu!\n", src_port.get_name().c_str(), @@ -1849,11 +1838,6 @@ void add_module_bus_nets(ModuleManager& module_manager, /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { - /* Create net only when des_port has a valid pin! */ - if (pin_id >= des_port.pins().size()) { - continue; - } - ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]); diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index 6cdf27fe8..28913e673 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -165,8 +165,7 @@ void add_module_bus_nets(ModuleManager& module_manager, const ModulePortId& src_module_port_id, const ModuleId& des_module_id, const size_t& des_instance_id, - const ModulePortId& des_module_port_id, - const bool& align_to_lsb = false); + const ModulePortId& des_module_port_id); } /* end namespace openfpga */ From 51f2e7f62536b622ec71ae7a312c6c2898b3614b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 16:28:03 -0600 Subject: [PATCH 180/330] [Test] Add multi-region memory bank test case to CI --- .travis/basic_reg_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 474667b84..a2c528d31 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -45,6 +45,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs @@ -95,3 +96,4 @@ echo -e "Testing K4N5 with pattern based local routing"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs end_section "OpenFPGA.TaskTun" +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs From 241ebf054a5a6e6b8962c7922a397c91524e32c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 16:29:46 -0600 Subject: [PATCH 181/330] [Test] Add a test case for validating fast configuration techniques on multi-region memory banks --- .../config/task.conf | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf new file mode 100644 index 000000000..342c3ae94 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 153b265a6dd15d03fd9401d089e03099e04390f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 16:32:05 -0600 Subject: [PATCH 182/330] [Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set --- .../k4_N4_40nm_bank_use_both_set_reset_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index 0fde86957..816c3e0a4 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -168,7 +168,7 @@ - + From 1ad591c08cd8e5a1a39fdff158d45a7776279cd8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 16:33:54 -0600 Subject: [PATCH 183/330] [Test] Add smart fast configuration test cases for multi-region memory banks to CI --- .travis/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index a2c528d31..e6e04412e 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -49,6 +49,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; From c2c384e24bb7478c9bfcc469421afb5014f2f0db Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Oct 2020 17:04:25 -0600 Subject: [PATCH 184/330] [Doc] update documentation about memory bank definition --- .../manual/arch_lang/config_protocol.rst | 11 ++++++----- .../manual/arch_lang/figures/memory_bank.png | Bin 0 -> 396651 bytes docs/source/manual/arch_lang/figures/sram.png | Bin 78120 -> 0 bytes 3 files changed, 6 insertions(+), 5 deletions(-) create mode 100644 docs/source/manual/arch_lang/figures/memory_bank.png delete mode 100644 docs/source/manual/arch_lang/figures/sram.png diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index a460ad1de..d52399cdf 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -115,8 +115,9 @@ When the decoder of sub block, e.g., the LUT, is enabled, each memory cells can Memory bank Example ~~~~~~~~~~~~~~~~~~~ -The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`. +The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_memory_bank`. It will use the circuit model defined in :numref:`fig_sram_blwl`. +Users can customized the number of memory banks to be used across the fabrics. By default, it will be only 1 memory bank. :numref:`fig_memory_bank` shows an example where 4 memory banks are defined. The more memory bank to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics. The organization of each configurable region can be customized through the fabric key (see details in :ref:`fabric_key`). .. code-block:: xml @@ -124,13 +125,13 @@ It will use the circuit model defined in :numref:`fig_sram_blwl`. -.. _fig_sram: +.. _fig_memory_bank: -.. figure:: figures/sram.png - :scale: 60% +.. figure:: figures/memory_bank.png + :scale: 30% :alt: map to buried treasure - Example of a memory organization using memory decoders + Example of (a) a memory organization using memory decoders; (b) single memory bank across the fabric; and (c) multiple memory banks across the fabric. .. note:: Memory-bank decoders does require a memory cell to have diff --git a/docs/source/manual/arch_lang/figures/memory_bank.png b/docs/source/manual/arch_lang/figures/memory_bank.png new file mode 100644 index 0000000000000000000000000000000000000000..7092e9d5ea03349c10805ba56f2ffb9e4b0788b0 GIT binary patch literal 396651 zcmb5W1yo$i(gunXAV3HKf)fZ3f;$YF;I0X7!QBRT2*H8{cZZMwgS(U9?(XjH18;L~ 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