Merge pull request #558 from lnis-uofu/config_enable
Fixed a bug in config_enable support for preconfigured testbenches
This commit is contained in:
commit
fed02d847a
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@ -237,6 +237,8 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
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std::vector<size_t> default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id));
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std::vector<size_t> default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id));
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/* For configuration done signals, we should enable them in preconfigured wrapper */
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/* For configuration done signals, we should enable them in preconfigured wrapper */
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if (fabric_global_ports.global_port_is_config_enable(global_port_id)) {
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if (fabric_global_ports.global_port_is_config_enable(global_port_id)) {
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VTR_LOG("Config-enable port '%s' is detected with default value '%ld'", module_global_pin.get_name().c_str(), fabric_global_ports.global_port_default_value(global_port_id));
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default_values.clear();
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default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id));
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default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id));
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}
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}
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print_verilog_wire_constant_values(fp, module_global_pin, default_values);
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print_verilog_wire_constant_values(fp, module_global_pin, default_values);
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@ -0,0 +1,196 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="16"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="CFGDSDFFR" prefix="CFGDSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="SE" size="1" is_global="true" default_val="0"/>
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<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
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<port type="input" prefix="config_done" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="SI" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="CFGQN" size="1"/>
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<port type="output" prefix="CFGQ" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO_CFGD" prefix="GPIO_CFGD" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="config_done" lib_name="CONFIG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
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<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="CFGDSDFFR" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="A" size="1"/>
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="CFGDSDFFR"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO_CFGD" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_tree"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
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<!-- End physical pb_type binding in complex block IO -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -438,6 +438,50 @@ assign QN = !Q;
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endmodule //End Of Module
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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// - a configure enable, when enabled the registered output will
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// be released to the CFGQ
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// - a configure done, when enable, the regsitered output will be released to the Q
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//-----------------------------------------------------
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module CFGDSDFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
|
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input D, // Data Input
|
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input SI, // Scan-chain input
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input CFGE, // Configure enable
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input CFG_DONE, // Configure done
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output Q, // Regular Q output
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output CFGQ, // Data Q output which is released when configure enable is activated
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output CFGQN // Data Qb output which is released when configure enable is activated
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);
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||||||
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//------------Internal Variables--------
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reg q_reg;
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wire QN;
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||||||
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|
||||||
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//-------------Code Starts Here---------
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||||||
|
always @ ( posedge CK or posedge RST)
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||||||
|
if (RST) begin
|
||||||
|
q_reg <= 1'b0;
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||||||
|
end else if (SE) begin
|
||||||
|
q_reg <= SI;
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||||||
|
end else begin
|
||||||
|
q_reg <= D;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign CFGQ = CFGE ? Q : 1'b0;
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||||||
|
assign CFGQN = CFGE ? QN : 1'b1;
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||||||
|
|
||||||
|
assign Q = CFG_DONE ? q_reg : 1'b0;
|
||||||
|
assign QN = CFG_DONE ? !Q : 1'b1;
|
||||||
|
|
||||||
|
endmodule //End Of Module
|
||||||
|
|
||||||
|
|
||||||
//-----------------------------------------------------
|
//-----------------------------------------------------
|
||||||
// Function : D-type flip-flop with
|
// Function : D-type flip-flop with
|
||||||
// - asynchronous active high reset
|
// - asynchronous active high reset
|
||||||
|
|
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@ -19,6 +19,24 @@ module GPIO (
|
||||||
assign PAD = DIR ? 1'bz : A;
|
assign PAD = DIR ? 1'bz : A;
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
//-----------------------------------------------------
|
||||||
|
// Function : A minimum general purpose I/O with config_done signal
|
||||||
|
// which can block signals during configuration phase
|
||||||
|
//-----------------------------------------------------
|
||||||
|
module GPIO_CFGD (
|
||||||
|
input CONFIG_DONE, // Control signal to block signals
|
||||||
|
input A, // Data output
|
||||||
|
output Y, // Data input
|
||||||
|
inout PAD, // bi-directional pad
|
||||||
|
input DIR // direction control
|
||||||
|
);
|
||||||
|
//----- when direction enabled, the signal is propagated from PAD to data input
|
||||||
|
assign Y = CONFIG_DONE ? (DIR ? PAD : 1'bz) : 1'bz;
|
||||||
|
//----- when direction is disabled, the signal is propagated from data out to pad
|
||||||
|
assign PAD = CONFIG_DONE ? (DIR ? 1'bz : A) : 1'bz;
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
//-----------------------------------------------------
|
//-----------------------------------------------------
|
||||||
// Function : A minimum input pad
|
// Function : A minimum input pad
|
||||||
//-----------------------------------------------------
|
//-----------------------------------------------------
|
||||||
|
|
|
@ -23,7 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s
|
||||||
run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
|
run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
|
||||||
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
|
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
|
||||||
run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
|
run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
|
||||||
run-task basic_tests/preconfig_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
|
run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io --debug --show_thread_logs
|
||||||
run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
|
run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
|
||||||
|
|
||||||
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
|
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
|
||||||
|
|
|
@ -17,7 +17,7 @@ fpga_flow=yosys_vpr
|
||||||
|
|
||||||
[OpenFPGA_SHELL]
|
[OpenFPGA_SHELL]
|
||||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
|
||||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml
|
||||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
Loading…
Reference in New Issue