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Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure

This commit is contained in:
Lalit Sharma 2021-11-12 01:46:06 -08:00
parent 7b611601fc
commit fe74c42252
3 changed files with 5 additions and 3 deletions
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4
CMakeLists.txt
View File

@ -231,6 +231,7 @@ include(CheckCXXCompilerFlag)
add_custom_target( add_custom_target(
yosys ALL yosys ALL
COMMAND $(MAKE) config-gcc COMMAND $(MAKE) config-gcc
COMMAND $(MAKE) clean
COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
COMMENT "Compile Yosys with given Makefile" COMMENT "Compile Yosys with given Makefile"
@ -241,7 +242,8 @@ add_custom_target(
# yosys-plugins compilation starts # yosys-plugins compilation starts
add_custom_target( add_custom_target(
yosys-plugins ALL yosys-plugins ALL
COMMAND $(MAKE) install YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install COMMAND $(MAKE) clean YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql"
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys
COMMENT "Compile Yosys-plugins with given Makefile" COMMENT "Compile Yosys-plugins with given Makefile"

2
Makefile
View File

@ -21,7 +21,7 @@ compile:
cd build && $(MAKE) cd build && $(MAKE)
clean: clean:
rm -rf build rm -rf build yosys/install
build/Makefile: build/Makefile:
make checkout make checkout

2
openfpga_flow/misc/qlf_yosys.ys
View File

@ -5,6 +5,6 @@ plugin -i ql-qlf
# Read verilog files # Read verilog files
${READ_VERILOG_FILE} ${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS} synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
write_verilog -noattr -nohex ${OUTPUT_VERILOG} write_verilog -noattr -nohex ${OUTPUT_VERILOG}