[core] code format

openfpga/src/annotation/append_clock_rr_graph.cpp

@@ -426,7 +426,8 @@ static void try_find_and_add_clock_track2ipin_node(
     if (grid_pin_idx == grid_type->num_pins) {
       continue;
     }
-    VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", grid_pin_idx);
+    VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n",
+             grid_pin_idx);
     RRNodeId des_node = rr_graph_view.node_lookup().find_node(
       layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side);
     if (rr_graph_view.valid_node(des_node)) {
@@ -473,9 +474,9 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(
   if (chan_type == CHANX) {
     /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */
     vtr::Point<size_t> bot_grid_coord(chan_coord.x(), chan_coord.y() + 1);
-    try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
+    try_find_and_add_clock_track2ipin_node(
-                                           layer, bot_grid_coord, BOTTOM,
+      des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, clk_ntwk,
-                                           clk_ntwk, clk_tree, clk_pin, verbose);
+      clk_tree, clk_pin, verbose);
 
     /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */
     vtr::Point<size_t> top_grid_coord(chan_coord.x(), chan_coord.y());
@@ -486,15 +487,15 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(
     VTR_ASSERT(chan_type == CHANY);
     /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */
     vtr::Point<size_t> left_grid_coord(chan_coord.x() + 1, chan_coord.y());
-    try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
+    try_find_and_add_clock_track2ipin_node(
-                                           layer, left_grid_coord, LEFT,
+      des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, clk_ntwk,
-                                           clk_ntwk, clk_tree, clk_pin, verbose);
+      clk_tree, clk_pin, verbose);
 
     /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */
     vtr::Point<size_t> right_grid_coord(chan_coord.x(), chan_coord.y());
-    try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
+    try_find_and_add_clock_track2ipin_node(
-                                           layer, right_grid_coord, RIGHT,
+      des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, clk_ntwk,
-                                           clk_ntwk, clk_tree, clk_pin, verbose);
+      clk_tree, clk_pin, verbose);
   }
 
   return des_nodes;
@@ -816,8 +817,7 @@ static void add_rr_graph_clock_edges(
  *******************************************************************/
 int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
                           RRClockSpatialLookup& clk_rr_lookup,
-                          const ClockNetwork& clk_ntwk,
+                          const ClockNetwork& clk_ntwk, const bool& verbose) {
-                          const bool& verbose) {
   vtr::ScopedStartFinishTimer timer(
     "Appending programmable clock network to routing resource graph");
 

openfpga/src/base/openfpga_pb_pin_fixup.cpp

@@ -59,8 +59,8 @@ static void update_cluster_pin_with_post_routing_results(
       VTR_ASSERT(class_inf.type == RECEIVER);
       rr_node_type = IPIN;
     }
-    std::vector<e_side> pin_sides =
+    std::vector<e_side> pin_sides = find_physical_tile_pin_side(
-      find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb);
+      physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb);
     /* As some grid has height/width offset, we may not have the pin on any side
      */
     if (0 == pin_sides.size()) {

openfpga/src/fabric/build_device_module.cpp

@@ -143,8 +143,7 @@ int build_device_module_graph(
     sram_model, fabric_tile, name_module_using_index, frame_view,
     compress_routing, duplicate_grid_pin, fabric_key,
     generate_random_fabric_key, group_config_block,
-    vpr_device_ctx.arch->perimeter_cb,
+    vpr_device_ctx.arch->perimeter_cb, verbose);
-    verbose);
 
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;

openfpga/src/fabric/build_top_module.cpp

@@ -58,8 +58,7 @@ int build_top_module(
   const bool& name_module_using_index, const bool& frame_view,
   const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
   const FabricKey& fabric_key, const bool& generate_random_fabric_key,
-  const bool& group_config_block,
+  const bool& group_config_block, const bool& perimeter_cb,
-  const bool& perimeter_cb,
   const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
 

openfpga/src/fabric/build_top_module.h

@@ -45,8 +45,7 @@ int build_top_module(
   const bool& name_module_using_index, const bool& frame_view,
   const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
   const FabricKey& fabric_key, const bool& generate_random_fabric_key,
-  const bool& group_config_block,
+  const bool& group_config_block, const bool& perimeter_cb,
-  const bool& perimeter_cb,
   const bool& verbose);
 
 } /* end namespace openfpga */

openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp

@@ -454,8 +454,7 @@ int build_top_module_fine_grained_child_instances(
   const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
   const bool& frame_view, const bool& compact_routing_hierarchy,
   const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& group_config_block,
+  const bool& group_config_block, const bool& perimeter_cb,
-  const bool& perimeter_cb,
   const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;

openfpga/src/fabric/build_top_module_child_fine_grained_instance.h

@@ -44,8 +44,7 @@ int build_top_module_fine_grained_child_instances(
   const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
   const bool& frame_view, const bool& compact_routing_hierarchy,
   const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& group_config_block,
+  const bool& group_config_block, const bool& perimeter_cb,
-  const bool& perimeter_cb,
   const bool& verbose);
 
 } /* end namespace openfpga */

openfpga/src/fabric/build_top_module_child_tile_instance.cpp

@@ -1530,8 +1530,8 @@ static int build_top_module_global_net_from_tile_modules(
         status = build_top_module_global_net_for_given_tile_module(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
-          vtr::Point<size_t>(ix, iy), NUM_SIDES, tile_instance_ids,
+          vtr::Point<size_t>(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile,
-          fabric_tile, perimeter_cb);
+          perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1600,7 +1600,8 @@ static int add_top_module_global_ports_from_tile_modules(
   const size_t& layer, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb,
   const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
-  const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) {
+  const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup,
+  const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   /* Add the global ports which are NOT yet added to the top-level module
@@ -1905,8 +1906,7 @@ int build_top_module_tile_child_instances(
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
   const bool& group_config_block, const bool& name_module_using_index,
-  const bool& perimeter_cb,
+  const bool& perimeter_cb, const bool& frame_view, const bool& verbose) {
-  const bool& frame_view, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   vtr::Matrix<size_t> tile_instance_ids;
   status = add_top_module_tile_instances(module_manager, top_module,

openfpga/src/fabric/build_top_module_child_tile_instance.h

@@ -44,8 +44,7 @@ int build_top_module_tile_child_instances(
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
   const bool& group_config_block, const bool& name_module_using_index,
-  const bool& perimeter_cb,
+  const bool& perimeter_cb, const bool& frame_view, const bool& verbose);
-  const bool& frame_view, const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fabric/build_top_module_connection.cpp

@@ -1171,7 +1171,8 @@ static int build_top_module_global_net_from_grid_modules(
         status = build_top_module_global_net_for_given_grid_module(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
-          vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb);
+          vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids,
+          perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1319,8 +1320,7 @@ int add_top_module_global_ports_from_grid_modules(
   const DeviceRRGSB& device_rr_gsb,
   const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
   const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
-  const RRClockSpatialLookup& rr_clock_lookup,
+  const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) {
-  const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   /* Add the global ports which are NOT yet added to the top-level module

openfpga/src/fabric/build_top_module_connection.h

@@ -42,8 +42,7 @@ int add_top_module_global_ports_from_grid_modules(
   const DeviceRRGSB& device_rr_gsb,
   const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
   const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
-  const RRClockSpatialLookup& rr_clock_lookup,
+  const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb);
-  const bool& perimeter_cb);
 
 void add_top_module_nets_prog_clock(ModuleManager& module_manager,
                                     const ModuleId& top_module,

openfpga/src/utils/openfpga_physical_tile_utils.cpp

@@ -40,9 +40,10 @@ std::vector<e_side> find_physical_tile_pin_side(
 
   /* For regular grid, we should have pin only one side!
    * I/O grids: VPR creates the grid with duplicated pins on every side
-   * - In regular cases: the expected side (only used side) will be on the opposite to the border
+   * - In regular cases: the expected side (only used side) will be on the
-   * side!
+   * opposite to the border side!
-   * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side
+   * - When perimeter cb is on, the expected sides can be on any sides except
+   * the border side. But we only expect 1 side
    */
   if (NUM_SIDES == border_side) {
     VTR_ASSERT(1 == pin_sides.size());
@@ -179,7 +180,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
     }
     if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
       VTR_LOG_ERROR(
-        "Invalid pin name '%s' whose subtile index is out of range, expect [%lu, "
+        "Invalid pin name '%s' whose subtile index is out of range, expect "
+        "[%lu, "
         "%lu]\n",
         pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high);
       exit(1);
@@ -205,7 +207,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
       /* Reach here, we get the port we want, return the accumulated index */
       size_t accumulated_pin_idx =
         sub_tile_port.absolute_first_pin_index +
-        (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) +
+        (sub_tile.num_phy_pins / sub_tile.capacity.total()) *
+          (tile_info.get_lsb() - sub_tile.capacity.low) +
         pin_info.get_lsb();
       return accumulated_pin_idx;
     }