From fdb85bba206cdd68fdf3e9ba940cbc1cbcc8c7b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 31 Jan 2023 14:05:19 -0800 Subject: [PATCH] [script] disable VTR no-warning build --- CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ca03e30c3..193ac953e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -84,7 +84,8 @@ set(WITH_YOSYS OFF CACHE BOOL "Enable building Yosys in Verilog-to-Routing") set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Routing") set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing") set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number") -set(VTR_ENABLE_STRICT_COMPILE ${OPENFPGA_ENABLE_STRICT_COMPILE} CACHE BOOL "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)") +# TODO: OpenFPGA and VPR has different requirements on no-warning build, e.g., on OS and compiler versions +#set(VTR_ENABLE_STRICT_COMPILE ${OPENFPGA_ENABLE_STRICT_COMPILE} CACHE BOOL "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)") # TCL file/lib required to link with SWIG generated wrapper if (OPENFPGA_WITH_SWIG)