diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v
index c27dbeebe..0cd5862c1 100644
--- a/openfpga_flow/VerilogNetlists/sram.v
+++ b/openfpga_flow/VerilogNetlists/sram.v
@@ -17,7 +17,7 @@ output outb // Data output
   reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl, wl) 
+  always @(bl or wl) 
   begin
     if (1'b1 == reset) begin 
       data <= 1'b0;
@@ -42,6 +42,84 @@ output outb // Data output
 
 endmodule
 
+module sram_blwl_set(
+input set, // Word line control signal
+input wl, // Word line control signal
+input bl, // Bit line control signal
+output out, // Data output
+output outb // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(bl or wl) 
+  begin
+    if (1'b1 == set) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign out = data;
+    assign outb = ~data;
+`else
+    assign out = 1'bZ;
+    assign outb = !out;
+`endif
+
+endmodule
+
+module sram_blwl_set_reset(
+input reset, // Word line control signal
+input set, // Word line control signal
+input wl, // Word line control signal
+input bl, // Bit line control signal
+output out, // Data output
+output outb // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(bl or wl) 
+  begin
+    if (1'b1 == reset) begin 
+      data <= 1'b0;
+    end else if (1'b1 == set) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign out = data;
+    assign outb = ~data;
+`else
+    assign out = 1'bZ;
+    assign outb = !out;
+`endif
+
+endmodule
+
+
 
 //------ Module: sram6T_blwl -----//
 //------ Verilog file: sram.v -----//