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[Lib] Add validator to check if a clock is constrained in simulation settings

This commit is contained in:
tangxifan 2021-10-06 11:48:23 -07:00
parent 82ed6b177b
commit fcb5470baa
3 changed files with 7 additions and 2 deletions
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4
libopenfpga/libarchopenfpga/src/simulation_setting.cpp
View File

@ -328,5 +328,9 @@ bool SimulationSetting::valid_clock_id(const SimulationClockId& clock_id) const
return ( size_t(clock_id) < clock_ids_.size() ) && ( clock_id == clock_ids_[clock_id] );
}
bool SimulationSetting::constrained_clock(const SimulationClockId& clock_id) const {
VTR_ASSERT(valid_clock_id(clock_id));
return 0. != clock_frequencies_[clock_id];
}
} /* namespace openfpga ends */

2
libopenfpga/libarchopenfpga/src/simulation_setting.h
View File

@ -139,6 +139,8 @@ class SimulationSetting {
public: /* Public Validators */
bool valid_signal_threshold(const float& threshold) const;
bool valid_clock_id(const SimulationClockId& clock_id) const;
/** @brief Validate if a given clock is constrained or not */
bool constrained_clock(const SimulationClockId& clock_id) const;
private: /* Internal data */
/* Operating clock frequency: the default clock frequency to be applied to users' implemetation on FPGA
* This will be stored in the x() part of vtr::Point

3
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
View File

@ -297,7 +297,7 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
float& sr_clock_period) {
for (const SimulationClockId& sim_clk : sim_settings.programming_shift_register_clocks()) {
/* Bypass all the clocks which does not match */
if (sim_settings.clock_port(sim_clk) == sr_clock_port) {
if (sim_settings.clock_port(sim_clk) == sr_clock_port && sim_settings.constrained_clock(sim_clk)) {
if (sr_clock_period > 0.5 * (1 / sim_settings.clock_frequency(sim_clk)) / timescale) {
VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s[Hz])! Shift register chain cannot load data completely!\n",
1. / (2. * sr_clock_period) / 1e6,
@ -367,7 +367,6 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(s
time_unit_to_string(1e6).c_str(),
wl_sr_clock_port.get_name().c_str());
if (CMD_EXEC_FATAL_ERROR == constrain_blwl_shift_register_clock_period_from_simulation_settings(sim_settings,
bl_sr_clock_port,
timescale,