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add stats for verilog modules

This commit is contained in:
tangxifan 2019-08-23 18:41:16 -06:00
parent 8eebca9daa
commit fcb31e4c24
3 changed files with 8 additions and 0 deletions
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5
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
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@ -15,6 +15,11 @@
/****************************************************************************** /******************************************************************************
* Public Accessors * Public Accessors
******************************************************************************/ ******************************************************************************/
/* Return number of modules */
size_t ModuleManager::num_modules() const {
return ids_.size();
}
/* Find the name of a module */ /* Find the name of a module */
std::string ModuleManager::module_name(const ModuleId& module_id) const { std::string ModuleManager::module_name(const ModuleId& module_id) const {
/* Validate the module_id */ /* Validate the module_id */

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
View File

@ -33,6 +33,7 @@ class ModuleManager {
}; };
public: /* Public Constructors */ public: /* Public Constructors */
public: /* Public accessors */ public: /* Public accessors */
size_t num_modules() const;
std::string module_name(const ModuleId& module_id) const; std::string module_name(const ModuleId& module_id) const;
std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const;
std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -420,6 +420,8 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
chomped_circuit_name, chomped_circuit_name,
*(Arch.spice) ); *(Arch.spice) );
vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules());
/* End time count */ /* End time count */
t_end = clock(); t_end = clock();