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OpenFPGA
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conf res

This commit is contained in:
alaindargelas 2024-03-05 10:15:01 -08:00
parent 70beaa6393 23e3e29019
commit fcaaba0e55
3 changed files with 177 additions and 160 deletions
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16
libs/libpcf/src/base/pcf2place.cpp
View File

@ -41,6 +41,8 @@ int pcf2place(const PcfData& pcf_data,
VTR_LOG("PCF basic check passed\n");
}
/* Map from location to net */
std::map<std::array<size_t, 3>, std::string> net_map;
/* Build the I/O place */
for (const PcfIoConstraintId& io_id : pcf_data.io_constraints()) {
/* Find the net name */
@ -102,6 +104,20 @@ int pcf2place(const PcfData& pcf_data,
continue;
}
std::array<size_t, 3> loc = {x, y, z};
auto itr = net_map.find(loc);
if (itr == net_map.end()) {
net_map.insert({loc, net});
} else {
VTR_LOG_ERROR(
"Illegal pin constraint: Two nets '%s' and '%s' are mapped to the I/O "
"pin '%s[%lu]' which belongs to the same coordinate (%ld, %ld, %ld)!\n",
itr->second.c_str(), net.c_str(), int_pin.get_name().c_str(),
int_pin.get_lsb(), x, y, z);
num_err++;
continue;
}
/* Add a fixed prefix to net namei, this is hard coded by VPR */
if (IoPinTable::OUTPUT == pin_direction) {
net = "out:" + net;

15
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -84,8 +84,8 @@ void print_verilog_testbench_fpga_instance(
module_manager.module_port(top_module, module_port_id);
/* Bypass dummy port: the port does not exist at core module */
if (io_name_map.fpga_top_port_is_dummy(module_port)) {
ModulePortId core_module_port =
module_manager.find_module_port(core_module, module_port.get_name());
ModulePortId core_module_port = module_manager.find_module_port(
core_module, module_port.get_name());
if (!module_manager.valid_module_port_id(core_module,
core_module_port)) {
/* Print the wire for the dummy port */
@ -132,7 +132,8 @@ void print_verilog_testbench_benchmark_instance(
const std::string& instance_name,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix, const std::string& output_port_postfix,
const std::string& input_port_postfix,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
@ -654,8 +655,8 @@ void print_verilog_testbench_check(
print_verilog_comment(
fp, std::string("----- Begin checking output vectors -------"));
std::vector<BasicPort> clock_ports =
generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(
clock_port_names, default_clock_name);
print_verilog_comment(fp,
std::string("----- Skip the first falling edge of "
@ -991,8 +992,8 @@ void print_verilog_testbench_shared_input_ports(
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
const bool& use_reg_port) {
const bool& include_clock_ports,
const std::string& shared_input_port_postfix, const bool& use_reg_port) {
/* Validate the file stream */
valid_file_stream(fp);

2
yosys

@ -1 +1 @@
Subproject commit 91fbd58980e87ad5dc0a5d37c049ffaf5ab243dd
Subproject commit 1e42b4f0f9cc1d2f4097ea632a93be3473b0c2f7