remove unused variable in sim info writer
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0852ef33c3
commit
fc164abd49
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@ -24,7 +24,6 @@
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********************************************************************/
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********************************************************************/
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void print_verilog_simulation_info(const std::string& simulation_ini_filename,
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void print_verilog_simulation_info(const std::string& simulation_ini_filename,
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const std::string& parent_dir,
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const std::string& parent_dir,
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const std::string& verilog_dir,
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const std::string& circuit_name,
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const std::string& circuit_name,
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const std::string& src_dir,
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const std::string& src_dir,
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const size_t& num_program_clock_cycles,
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const size_t& num_program_clock_cycles,
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@ -5,7 +5,6 @@
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void print_verilog_simulation_info(const std::string& simulation_ini_filename,
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void print_verilog_simulation_info(const std::string& simulation_ini_filename,
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const std::string& parent_dir,
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const std::string& parent_dir,
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const std::string& verilog_dir,
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const std::string& circuit_name,
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const std::string& circuit_name,
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const std::string& src_dir,
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const std::string& src_dir,
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const size_t& num_program_clock_cycles,
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const size_t& num_program_clock_cycles,
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@ -437,7 +437,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
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/* Print exchangeable files which contains simulation settings */
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/* Print exchangeable files which contains simulation settings */
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print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path),
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print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path),
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std::string(format_dir_path(chomped_parent_dir)),
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std::string(format_dir_path(chomped_parent_dir)),
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std::string(msim_dir_path),
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std::string(chomped_circuit_name),
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std::string(chomped_circuit_name),
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std::string(src_dir_path),
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std::string(src_dir_path),
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bitstream_manager.bits().size(),
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bitstream_manager.bits().size(),
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