From fbe5ae6bd359b4c2cf12bb14c784cbaad32f1cfe Mon Sep 17 00:00:00 2001
From: chungshien-chai <chungshien.chai@gmail.com>
Date: Fri, 26 Jul 2024 02:18:08 -0700
Subject: [PATCH] Update test

---
 .../device_4x4_PathBitSetting/config/bitstream_annotation.xml   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml
index 19ed76fe4..24b5fa8f6 100644
--- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml
+++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml
@@ -5,5 +5,5 @@
 -->
 <openfpga_bitstream_setting>
   <bit value="0" path="fpga_top.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
-  <bit value="1" path="fpga_top.grid_io_bottom_3__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
+  <bit value="0" path="fpga_top.grid_io_bottom_3__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
 </openfpga_bitstream_setting>