diff --git a/docs/source/manual/openfpga_flow/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst
index 095889373..f923c1da1 100644
--- a/docs/source/manual/openfpga_flow/run_fpga_task.rst
+++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst
@@ -265,6 +265,11 @@ Synthesis Parameter Sections
     the source Verilog design for ``bench_label`` benchmark to be used
     while verification.
 
+.. option:: bench<bench_label>_read_verilog_options=<Options>
+
+    This option defines the ``read_verilog`` command options for ``bench_label`` benchmark.
+    If all benchmarks share the same options then ``bench_read_verilog_options_common`` can be used to define common options.
+
 Script Parameter Sections
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 9ce067a73..050653236 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -531,9 +531,9 @@ def create_yosys_params():
                 shlex.quote(eachdir) for eachdir in ys_params["VERIFIC_LIBRARY_DIR"].split(",")])
         try:
             for param, value in ys_params.items():
-                if param.startswith("LIB_NAME"):
-                    index = param[len("LIB_NAME"):]
-                    src_param = "LIB_SRC" + index
+                if param.startswith("VERIFIC_READ_LIB_NAME"):
+                    index = param[len("VERIFIC_READ_LIB_NAME"):]
+                    src_param = "VERIFIC_READ_LIB_SRC" + index
                     if src_param in ys_params:
                         src_files = []
                         for name in ys_params[src_param].split(","):