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start adding submodules of local encoders to multiplexer

This commit is contained in:
tangxifan 2019-08-02 16:22:52 -06:00
parent 33f3a991b5
commit fb2ca66ce9
8 changed files with 78 additions and 28 deletions
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16
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h
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@ -5,16 +5,20 @@
#include "my_free_fwd.h" #include "my_free_fwd.h"
void InitSpiceMeasParams(t_spice_meas_params* meas_params); void InitSpiceMeasParams(t_spice_meas_params* meas_params);
void FreeSpiceMeasParams(t_spice_meas_params* meas_params); void FreeSpiceMeasParams();
void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params); void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params);
void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params); void FreeSpiceStimulateParams();
void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params);
void FreeSpiceVariationParams();
void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params);
void FreeSpiceMonteCarloParams();
void InitSpiceParams(t_spice_params* spice_params); void InitSpiceParams(t_spice_params* spice_params);
void FreeSpiceParams(t_spice_params* params); void FreeSpiceParams();
void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist); void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist);
void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer); void FreeSpiceModelBuffer();
void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic); void FreeSpiceModelPassGateLogic();
void FreeSpiceModelPort(t_spice_model_port* spice_model_port); void FreeSpiceModelPort(t_spice_model_port* spice_model_port);
void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param); void FreeSpiceModelWireParam();
void FreeSpiceModel(t_spice_model* spice_model); void FreeSpiceModel(t_spice_model* spice_model);
void InitSpice(t_spice* spice); void InitSpice(t_spice* spice);
void FreeSpice(t_spice* spice); void FreeSpice(t_spice* spice);

3
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h
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@ -96,7 +96,7 @@ enum e_sram_orgz {
SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */
SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */
SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */
SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */
}; };
enum e_spice_accuracy_type { enum e_spice_accuracy_type {
@ -274,6 +274,7 @@ struct s_spice_model_mux {
boolean add_const_input; boolean add_const_input;
int const_input_val; int const_input_val;
boolean advanced_rram_design; boolean advanced_rram_design;
boolean local_encoder; /* Define if a local encoder should be added to this mux */
}; };
struct s_spice_model_lut { struct s_spice_model_lut {

4
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
View File

@ -600,6 +600,10 @@ static void ProcessSpiceModelMUX(ezxml_t Node,
mux_info->advanced_rram_design = GetBooleanProperty(Node,"advanced_rram_design", FALSE, FALSE); mux_info->advanced_rram_design = GetBooleanProperty(Node,"advanced_rram_design", FALSE, FALSE);
ezxml_set_attr(Node, "advanced_rram_design", NULL); ezxml_set_attr(Node, "advanced_rram_design", NULL);
/* Specify if should use a local encoder for this multiplexer */
mux_info->local_encoder = GetBooleanProperty(Node, "local_encoder", FALSE, FALSE);
ezxml_set_attr(Node, "local_encoder", NULL);
return; return;
} }

26
vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.c
View File

@ -41,7 +41,7 @@ void InitSpiceMeasParams(t_spice_meas_params* meas_params) {
return; return;
} }
void FreeSpiceMeasParams(t_spice_meas_params* meas_params) { void FreeSpiceMeasParams() {
return; return;
} }
@ -64,7 +64,7 @@ void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {
return; return;
} }
void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) { void FreeSpiceStimulateParams() {
return; return;
} }
@ -74,7 +74,7 @@ void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params)
mc_variation_params->num_sigma = 1; mc_variation_params->num_sigma = 1;
} }
void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) { void FreeSpiceVariationParams() {
return; return;
} }
@ -86,7 +86,7 @@ void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {
return; return;
} }
void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) { void FreeSpiceMonteCarloParams() {
return; return;
} }
@ -110,7 +110,7 @@ void InitSpiceParams(t_spice_params* params) {
return; return;
} }
void FreeSpiceParams(t_spice_params* params) { void FreeSpiceParams() {
return; return;
} }
@ -121,12 +121,12 @@ void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {
return; return;
} }
void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) { void FreeSpiceModelBuffer() {
return; return;
} }
void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) { void FreeSpiceModelPassGateLogic() {
return; return;
} }
@ -137,8 +137,7 @@ void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {
return; return;
} }
void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) { void FreeSpiceModelWireParam() {
return; return;
} }
@ -152,14 +151,14 @@ void FreeSpiceModel(t_spice_model* spice_model) {
spice_model->include_netlist = NULL; spice_model->include_netlist = NULL;
/* Free the buffers */ /* Free the buffers */
FreeSpiceModelBuffer(spice_model->input_buffer); FreeSpiceModelBuffer();
FreeSpiceModelBuffer(spice_model->output_buffer); FreeSpiceModelBuffer();
my_free(spice_model->input_buffer); my_free(spice_model->input_buffer);
my_free(spice_model->output_buffer); my_free(spice_model->output_buffer);
spice_model->input_buffer = NULL; spice_model->input_buffer = NULL;
spice_model->output_buffer = NULL; spice_model->output_buffer = NULL;
FreeSpiceModelPassGateLogic(spice_model->pass_gate_logic); FreeSpiceModelPassGateLogic();
my_free(spice_model->pass_gate_logic); my_free(spice_model->pass_gate_logic);
spice_model->pass_gate_logic = NULL; spice_model->pass_gate_logic = NULL;
@ -173,7 +172,7 @@ void FreeSpiceModel(t_spice_model* spice_model) {
/* Free wire parameters */ /* Free wire parameters */
if (NULL != spice_model->wire_param) { if (NULL != spice_model->wire_param) {
FreeSpiceModelWireParam(spice_model->wire_param); FreeSpiceModelWireParam();
my_free(spice_model->wire_param); my_free(spice_model->wire_param);
spice_model->wire_param = NULL; spice_model->wire_param = NULL;
} }
@ -220,6 +219,7 @@ void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {
return; return;
} }
static
void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) { void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {
my_free(sram_inf_orgz->spice_model_name); my_free(sram_inf_orgz->spice_model_name);

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c
View File

@ -199,6 +199,9 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model,
exit(1); exit(1);
} }
/* When a local encoder is added
*/
/* Free */ /* Free */
return num_sram_bits; return num_sram_bits;

45
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -34,8 +34,11 @@
#include "verilog_pbtypes.h" #include "verilog_pbtypes.h"
#include "verilog_decoder.h" #include "verilog_decoder.h"
#include "verilog_submodules.h"
/***** Subroutines *****/ /***** Subroutines *****/
static
void dump_verilog_submodule_timing(FILE* fp, void dump_verilog_submodule_timing(FILE* fp,
t_spice_model* cur_spice_model) { t_spice_model* cur_spice_model) {
int iport, ipin, iedge; int iport, ipin, iedge;
@ -85,6 +88,7 @@ void dump_verilog_submodule_timing(FILE* fp,
return; return;
} }
static
void dump_verilog_submodule_signal_init(FILE* fp, void dump_verilog_submodule_signal_init(FILE* fp,
t_spice_model* cur_spice_model) { t_spice_model* cur_spice_model) {
int iport; int iport;
@ -124,6 +128,7 @@ void dump_verilog_submodule_signal_init(FILE* fp,
/* Dump a module of inverter or buffer or tapered buffer */ /* Dump a module of inverter or buffer or tapered buffer */
static
void dump_verilog_invbuf_module(FILE* fp, void dump_verilog_invbuf_module(FILE* fp,
t_spice_model* invbuf_spice_model) { t_spice_model* invbuf_spice_model) {
int ipin, iport, port_cnt; int ipin, iport, port_cnt;
@ -344,6 +349,7 @@ void dump_verilog_invbuf_module(FILE* fp,
} }
/* Dump a module of pass-gate logic */ /* Dump a module of pass-gate logic */
static
void dump_verilog_passgate_module(FILE* fp, void dump_verilog_passgate_module(FILE* fp,
t_spice_model* passgate_spice_model) { t_spice_model* passgate_spice_model) {
int iport; int iport;
@ -448,6 +454,7 @@ void dump_verilog_passgate_module(FILE* fp,
} }
/* Dump a module of pass-gate logic */ /* Dump a module of pass-gate logic */
static
void dump_verilog_gate_module(FILE* fp, void dump_verilog_gate_module(FILE* fp,
t_spice_model* gate_spice_model) { t_spice_model* gate_spice_model) {
int iport, ipin, jport, jpin; int iport, ipin, jport, jpin;
@ -568,10 +575,10 @@ void dump_verilog_gate_module(FILE* fp,
* 1. inverters * 1. inverters
* 2. buffers * 2. buffers
* 3. pass-gate logics */ * 3. pass-gate logics */
static
void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir, void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir,
int num_spice_model, int num_spice_model,
t_spice_model* spice_models, t_spice_model* spice_models) {
t_syn_verilog_opts fpga_verilog_opts) {
int imodel; int imodel;
char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name); char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name);
FILE* fp = NULL; FILE* fp = NULL;
@ -616,6 +623,7 @@ void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir,
} }
/* Dump a CMOS MUX basis module */ /* Dump a CMOS MUX basis module */
static
void dump_verilog_cmos_mux_one_basis_module(FILE* fp, void dump_verilog_cmos_mux_one_basis_module(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
int mux_size, int mux_size,
@ -906,6 +914,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp,
/* Dump a RRAM MUX basis module */ /* Dump a RRAM MUX basis module */
static
void dump_verilog_rram_mux_one_basis_module(FILE* fp, void dump_verilog_rram_mux_one_basis_module(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
int num_input_basis_subckt, int num_input_basis_subckt,
@ -1021,6 +1030,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp,
} }
/* Print a basis submodule */ /* Print a basis submodule */
static
void dump_verilog_mux_one_basis_module(FILE* fp, void dump_verilog_mux_one_basis_module(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
int mux_size, int mux_size,
@ -1073,6 +1083,7 @@ void dump_verilog_mux_one_basis_module(FILE* fp,
/** /**
* Dump a verilog module for the basis circuit of a MUX * Dump a verilog module for the basis circuit of a MUX
*/ */
static
void dump_verilog_mux_basis_module(FILE* fp, void dump_verilog_mux_basis_module(FILE* fp,
t_spice_mux_model* spice_mux_model) { t_spice_mux_model* spice_mux_model) {
/** Act depends on the structure of MUX /** Act depends on the structure of MUX
@ -1165,6 +1176,7 @@ void dump_verilog_mux_basis_module(FILE* fp,
return; return;
} }
static
void dump_verilog_cmos_mux_tree_structure(FILE* fp, void dump_verilog_cmos_mux_tree_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
t_spice_model spice_model, t_spice_model spice_model,
@ -1195,7 +1207,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
inter_buf_loc[i] = FALSE; inter_buf_loc[i] = FALSE;
} }
if (NULL != spice_model.lut_intermediate_buffer->location_map) { if (NULL != spice_model.lut_intermediate_buffer->location_map) {
assert (spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map)); assert ((size_t)spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map));
/* For intermediate buffers */ /* For intermediate buffers */
for (i = 0; i < spice_mux_arch.num_level - 1; i++) { for (i = 0; i < spice_mux_arch.num_level - 1; i++) {
if ('1' == spice_model.lut_intermediate_buffer->location_map[i]) { if ('1' == spice_model.lut_intermediate_buffer->location_map[i]) {
@ -1404,6 +1416,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
char* mux_special_basis_subckt_name, char* mux_special_basis_subckt_name,
@ -1541,6 +1554,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
t_spice_model spice_model, t_spice_model spice_model,
@ -1622,6 +1636,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_cmos_mux_submodule(FILE* fp, void dump_verilog_cmos_mux_submodule(FILE* fp,
int mux_size, int mux_size,
t_spice_model spice_model, t_spice_model spice_model,
@ -1927,6 +1942,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
* However I use another function, because in future the internal structure may change. * However I use another function, because in future the internal structure may change.
* We will suffer less software problems. * We will suffer less software problems.
*/ */
static
void dump_verilog_rram_mux_tree_structure(FILE* fp, void dump_verilog_rram_mux_tree_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
t_spice_model spice_model, t_spice_model spice_model,
@ -1995,6 +2011,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_rram_mux_multilevel_structure(FILE* fp, void dump_verilog_rram_mux_multilevel_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
char* mux_special_basis_subckt_name, char* mux_special_basis_subckt_name,
@ -2095,6 +2112,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_rram_mux_onelevel_structure(FILE* fp, void dump_verilog_rram_mux_onelevel_structure(FILE* fp,
char* mux_basis_subckt_name, char* mux_basis_subckt_name,
t_spice_model spice_model, t_spice_model spice_model,
@ -2133,6 +2151,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp,
return; return;
} }
static
void dump_verilog_rram_mux_submodule(FILE* fp, void dump_verilog_rram_mux_submodule(FILE* fp,
int mux_size, int mux_size,
t_spice_model spice_model, t_spice_model spice_model,
@ -2366,6 +2385,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
} }
/* Dump a memory submodule for the MUX */ /* Dump a memory submodule for the MUX */
static
void dump_verilog_cmos_mux_mem_submodule(FILE* fp, void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
int mux_size, int mux_size,
t_spice_model spice_model, t_spice_model spice_model,
@ -2428,6 +2448,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
* 3. output ports * 3. output ports
* 4. bl/wl ports * 4. bl/wl ports
*/ */
/* Local Encoding support */
dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping)); dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping));
fprintf(fp, ");\n"); fprintf(fp, ");\n");
@ -2453,6 +2474,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp,
* We always dump a basis submodule for a MUX * We always dump a basis submodule for a MUX
* whatever structure it is: one-level, two-level or multi-level * whatever structure it is: one-level, two-level or multi-level
*/ */
static
void dump_verilog_mux_mem_module(FILE* fp, void dump_verilog_mux_mem_module(FILE* fp,
t_spice_mux_model* spice_mux_model, t_spice_mux_model* spice_mux_model,
bool is_explicit_mapping) { bool is_explicit_mapping) {
@ -2506,6 +2528,7 @@ void dump_verilog_mux_mem_module(FILE* fp,
* We always dump a basis submodule for a MUX * We always dump a basis submodule for a MUX
* whatever structure it is: one-level, two-level or multi-level * whatever structure it is: one-level, two-level or multi-level
*/ */
static
void dump_verilog_mux_module(FILE* fp, void dump_verilog_mux_module(FILE* fp,
t_spice_mux_model* spice_mux_model, t_spice_mux_model* spice_mux_model,
bool is_explicit_mapping) { bool is_explicit_mapping) {
@ -2568,7 +2591,7 @@ void dump_verilog_mux_module(FILE* fp,
/*** Top-level function *****/ /*** Top-level function *****/
/* We should count how many multiplexers with different sizes are needed */ /* We should count how many multiplexers with different sizes are needed */
static
void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* submodule_dir, char* submodule_dir,
@ -2696,6 +2719,7 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info,
return; return;
} }
static
void dump_verilog_wire_module(FILE* fp, void dump_verilog_wire_module(FILE* fp,
char* wire_subckt_name, char* wire_subckt_name,
t_spice_model verilog_model) { t_spice_model verilog_model) {
@ -2765,6 +2789,7 @@ void dump_verilog_wire_module(FILE* fp,
} }
/* Dump one module of a LUT */ /* Dump one module of a LUT */
static
void dump_verilog_submodule_one_lut(FILE* fp, void dump_verilog_submodule_one_lut(FILE* fp,
t_spice_model* verilog_model, t_spice_model* verilog_model,
bool is_explicit_mapping) { bool is_explicit_mapping) {
@ -3203,6 +3228,7 @@ void dump_verilog_submodule_one_lut(FILE* fp,
} }
/* Dump one module of a LUT */ /* Dump one module of a LUT */
static
void dump_verilog_submodule_one_mem(FILE* fp, void dump_verilog_submodule_one_mem(FILE* fp,
t_spice_model* verilog_model) { t_spice_model* verilog_model) {
int iport, ipin, pin_index; int iport, ipin, pin_index;
@ -3275,6 +3301,7 @@ void dump_verilog_submodule_one_mem(FILE* fp,
} }
/* Dump verilog top-level module for LUTs */ /* Dump verilog top-level module for LUTs */
static
void dump_verilog_submodule_luts(char* verilog_dir, void dump_verilog_submodule_luts(char* verilog_dir,
char* submodule_dir, char* submodule_dir,
int num_spice_model, int num_spice_model,
@ -3317,6 +3344,7 @@ void dump_verilog_submodule_luts(char* verilog_dir,
} }
/* Dump a submodule which is a constant vdd */ /* Dump a submodule which is a constant vdd */
static
void dump_verilog_hard_wired_vdd(FILE* fp, void dump_verilog_hard_wired_vdd(FILE* fp,
t_spice_model verilog_model) { t_spice_model verilog_model) {
int num_output_port = 0; int num_output_port = 0;
@ -3349,6 +3377,7 @@ void dump_verilog_hard_wired_vdd(FILE* fp,
} }
/* Dump a submodule which is a constant vdd */ /* Dump a submodule which is a constant vdd */
static
void dump_verilog_hard_wired_gnd(FILE* fp, void dump_verilog_hard_wired_gnd(FILE* fp,
t_spice_model verilog_model) { t_spice_model verilog_model) {
int num_output_port = 0; int num_output_port = 0;
@ -3380,6 +3409,7 @@ void dump_verilog_hard_wired_gnd(FILE* fp,
return; return;
} }
static
void dump_verilog_submodule_wires(char* verilog_dir, void dump_verilog_submodule_wires(char* verilog_dir,
char* subckt_dir, char* subckt_dir,
int num_segments, int num_segments,
@ -3461,6 +3491,7 @@ void dump_verilog_submodule_wires(char* verilog_dir,
return; return;
} }
static
void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* submodule_dir, char* submodule_dir,
@ -3581,6 +3612,7 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info,
/* Print a non-global port for the template */ /* Print a non-global port for the template */
static
void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt, void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt,
t_spice_model* cur_spice_model, t_spice_model* cur_spice_model,
enum e_spice_model_port_type port_type) { enum e_spice_model_port_type port_type) {
@ -3607,6 +3639,7 @@ void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt,
} }
/* Give a template for a user-defined module */ /* Give a template for a user-defined module */
static
void dump_one_verilog_template_module(FILE* fp, void dump_one_verilog_template_module(FILE* fp,
t_spice_model* cur_spice_model) { t_spice_model* cur_spice_model) {
int iport; int iport;
@ -3663,6 +3696,7 @@ void dump_one_verilog_template_module(FILE* fp,
} }
/* Give a template of all the submodules that are user-defined */ /* Give a template of all the submodules that are user-defined */
static
void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* submodule_dir, char* submodule_dir,
@ -3714,8 +3748,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n");
dump_verilog_submodule_essentials(verilog_dir, submodule_dir, dump_verilog_submodule_essentials(verilog_dir, submodule_dir,
Arch.spice->num_spice_model, Arch.spice->num_spice_model,
Arch.spice->spice_models, Arch.spice->spice_models);
fpga_verilog_opts);
/* 1. MUXes */ /* 1. MUXes */
vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n");

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h
View File

@ -1,7 +1,9 @@
#ifndef VERILOG_SUBMODULES_H
#define VERILOG_SUBMODULES_H
void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* submodule_dir, char* submodule_dir,
t_arch Arch, t_arch Arch,
t_det_routing_arch* routing_arch, t_det_routing_arch* routing_arch,
t_syn_verilog_opts fpga_verilog_opts); t_syn_verilog_opts fpga_verilog_opts);
#endif

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -3029,7 +3029,10 @@ int dump_verilog_mem_module_one_port_map(FILE* fp,
return cnt; return cnt;
} }
/* Output the ports of a SRAM MUX */ /*
* Dump the port map of a memory module
* which consist of a number of SRAMs/SCFFs etc.
*/
void dump_verilog_mem_module_port_map(FILE* fp, void dump_verilog_mem_module_port_map(FILE* fp,
t_spice_model* mem_model, t_spice_model* mem_model,
boolean dump_port_type, boolean dump_port_type,