From fae5e1dfdfb106d1e0d97112684fdd6de6eeb738 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Jun 2021 15:16:37 -0600 Subject: [PATCH] [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' --- .../behavioral_verilog_example_script.openfpga | 4 ++-- .../bitstream_setting_example_script.openfpga | 4 ++-- .../configuration_chain_example_script.openfpga | 4 ++-- .../duplicated_grid_pin_example_script.openfpga | 4 ++-- .../openfpga_shell_scripts/example_script.openfpga | 4 ++-- .../example_without_ace_script.openfpga | 4 ++-- .../fix_device_example_script.openfpga | 4 ++-- ...e_clock_bitstream_setting_example_script.openfpga | 4 ++-- ..._device_global_tile_clock_example_script.openfpga | 4 ++-- ...x_device_route_chan_width_example_script.openfpga | 4 ++-- .../fix_heterogeneous_device_example_script.openfpga | 4 ++-- .../flatten_routing_example_script.openfpga | 4 ++-- .../generate_secure_fabric_example_script.openfpga | 4 ++-- ...te_secure_fabric_from_key_example_script.openfpga | 4 ++-- .../generate_testbench_example_script.openfpga | 4 ++-- .../global_tile_clock_example_script.openfpga | 4 ++-- .../global_tile_multiclock_example_script.openfpga | 4 ++-- .../implicit_verilog_example_script.openfpga | 4 ++-- .../iverilog_example_script.openfpga | 4 ++-- .../mcnc_example_script.openfpga | 4 ++-- .../openfpga_shell_scripts/rename_scripts.sh | 12 ++++++++++-- .../skywater_tapeout_example_script.openfpga | 4 ++-- .../verilog_default_net_type_example_script.openfpga | 4 ++-- 23 files changed, 54 insertions(+), 46 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga index cf614678e..be124317b 100644 --- a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index 2d4820510..d0e0d69e2 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga index 34e56c3b9..00944653e 100644 --- a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga index cf9cbd8b5..55c54adb7 100644 --- a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga @@ -55,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga index 71e6fd224..a31f81948 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga index 61c5ea8af..e614455cf 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga index 94a9a41c5..594d2e21b 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga index ea4f9912e..4a826bffe 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga index c40e79c79..1e1db546d 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index fe7679f65..7ca431e92 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga index 79430e976..9f2742315 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga index 4511ba34d..2fc56e4c7 100644 --- a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga index 571ceee8f..6efc2baa5 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga index 857b20981..4dd7f21c3 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga @@ -59,8 +59,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index 19487e48b..b0322f105 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -52,8 +52,8 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index bc56dc8ee..db51ffe15 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -58,8 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index 5fe8cd4b5..ff0ba8d81 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -62,8 +62,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index 9a32a86eb..31296021f 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga index d44e57a24..1741f3011 100644 --- a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga index 7f2984f96..78daebb4b 100644 --- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga @@ -54,8 +54,8 @@ write_fabric_verilog --file ./SRC \ # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh index 6b568e5d8..c222fa6d5 100644 --- a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh +++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh @@ -1,4 +1,12 @@ foreach i (*.openfpga) - sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i - sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +# sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i +# sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +end + +foreach i (*.openfpga) + sed -i 's/--support_icarus_simulator//g' $i +end + +foreach i (*.openfpga) + sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i end diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga index 7cfe311f3..7dd793dbe 100644 --- a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga index fab25be5a..3dc4da3da 100644 --- a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga @@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_fabric_wrapper --file ./SRC --support_icarus_simulator --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --support_icarus_simulator --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here