[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
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@ -272,6 +272,11 @@ void print_verilog_top_testbench_global_clock_ports_stimuli(std::fstream& fp,
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ModulePortId module_global_port = fabric_global_port_info.global_module_port(fabric_global_port);
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VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
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/* Skip shift register clocks, they are handled in another way */
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if (true == fabric_global_port_info.global_port_is_shift_register(fabric_global_port)) {
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continue;
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}
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BasicPort stimuli_clock_port;
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if (true == fabric_global_port_info.global_port_is_prog(fabric_global_port)) {
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stimuli_clock_port.set_name(std::string(TOP_TB_PROG_CLOCK_PORT_NAME));
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@ -563,6 +568,11 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
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fabric_global_port_info,
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simulation_parameters);
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print_verilog_top_testbench_global_shift_register_clock_ports_stimuli(fp,
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module_manager,
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top_module,
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fabric_global_port_info);
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print_verilog_top_testbench_global_config_done_ports_stimuli(fp,
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module_manager,
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top_module,
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@ -199,6 +199,46 @@ void print_verilog_top_testbench_ql_memory_bank_port(std::fstream& fp,
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fp << ";" << std::endl;
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}
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void print_verilog_top_testbench_global_shift_register_clock_ports_stimuli(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const FabricGlobalPortInfo& fabric_global_port_info) {
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/* Validate the file stream */
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valid_file_stream(fp);
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/* Connect global clock ports to shift-register programming clock signal */
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for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) {
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/* Only care shift register clocks */
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if (false == fabric_global_port_info.global_port_is_clock(fabric_global_port)
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|| false == fabric_global_port_info.global_port_is_shift_register(fabric_global_port)
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|| false == fabric_global_port_info.global_port_is_prog(fabric_global_port)) {
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continue;
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}
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/* Find the module port */
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ModulePortId module_global_port = fabric_global_port_info.global_module_port(fabric_global_port);
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VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
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BasicPort stimuli_clock_port;
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if (true == fabric_global_port_info.global_port_is_bl(fabric_global_port)) {
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stimuli_clock_port.set_name(std::string(TOP_TB_BL_SHIFT_REGISTER_CLOCK_PORT_NAME));
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stimuli_clock_port.set_width(1);
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} else {
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VTR_ASSERT(true == fabric_global_port_info.global_port_is_wl(fabric_global_port));
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stimuli_clock_port.set_name(std::string(TOP_TB_BL_SHIFT_REGISTER_CLOCK_PORT_NAME));
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stimuli_clock_port.set_width(1);
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}
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for (const size_t& pin : module_manager.module_port(top_module, module_global_port).pins()) {
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BasicPort global_port_to_connect(module_manager.module_port(top_module, module_global_port).get_name(), pin, pin);
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print_verilog_wire_connection(fp, global_port_to_connect,
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stimuli_clock_port,
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1 == fabric_global_port_info.global_port_default_value(fabric_global_port));
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}
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}
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}
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/**
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* @brief Generate the Verilog codes for a shift register clocks that controls BL/WL protocols
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*/
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@ -34,6 +34,14 @@ void print_verilog_top_testbench_ql_memory_bank_port(std::fstream& fp,
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const ModuleId& top_module,
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const ConfigProtocol& config_protocol);
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/**
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* @brief Generate the Verilog codes that connect shift register clock stimuli to FPGA ports
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*/
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void print_verilog_top_testbench_global_shift_register_clock_ports_stimuli(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& top_module,
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const FabricGlobalPortInfo& fabric_global_port_info);
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/**
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* @brief Generate the Verilog codes that generate stimuli waveforms for BL/WL protocols
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*/
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