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[Tool] Remove exceptions on outputing verilog port with lsb=0

This commit is contained in:
tangxifan 2021-03-17 20:27:08 -06:00
parent c8d41b4e69
commit fa11410425
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
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@ -488,7 +488,7 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
&& (0 == port_info.get_lsb()) && (0 == port_info.get_lsb())
&& (1 == port_info.get_origin_port_width())) { && (1 == port_info.get_origin_port_width())) {
size_str.clear(); size_str.clear();
} else if ((1 == port_info.get_width()) && (0 != port_info.get_lsb())) { } else if ((1 == port_info.get_width())) {
size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
} }
verilog_line = port_info.get_name() + size_str; verilog_line = port_info.get_name() + size_str;