diff --git a/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
index 10bc1d491..4351799ec 100644
--- a/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --{OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml/config/task.conf b/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml/config/task.conf
index 1414280b1..a8e41330d 100644
--- a/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 openfpga_build_fabric_option=
 openfpga_write_gsb_option=
 
diff --git a/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_compress_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_compress_routing/config/task.conf
index 1460d94f2..05c3cfca0 100644
--- a/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_compress_routing/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_compress_routing/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 openfpga_build_fabric_option=--compress_routing
 openfpga_write_gsb_option=
 
diff --git a/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml/config/task.conf b/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml/config/task.conf
index cb5ef2bd5..96b57eb0c 100644
--- a/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 openfpga_build_fabric_option=
 openfpga_write_gsb_option=--unique
 
diff --git a/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing/config/task.conf
index b7d266430..3f9fed5e9 100644
--- a/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 openfpga_build_fabric_option=--compress_routing
 openfpga_write_gsb_option=--unique
 
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
index 214e81e9a..2caa8b1ba 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@@ -77,6 +77,13 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM