Update dpram16k.v

2022-10-26 16:27:30 +03:00 · 2022-10-26 16:27:30 +03:00 · f8b170ba75
parent a795c943a9
commit f8b170ba75
1 changed files with 2 additions and 2 deletions
--- a/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
@ -14,7 +14,7 @@ module dpram_512x32 (
 	input[0:31] d_in,
 	output[0:31] d_out );

-		dual_port_sram memory_0 (
+		dpram_512x32_core memory_0 (
 			.wclk		(clk),
 			.wen		(wen),
 			.waddr		(waddr),
@ -26,7 +26,7 @@ module dpram_512x32 (

 endmodule

-module dual_port_sram (
+module dpram_512x32_core (
 	input wclk,
 	input wen,
 	input[0:9] waddr,