diff --git a/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml
new file mode 100644
index 000000000..dd5cca16d
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+++ b/openfpga_flow/vpr_arch/k4_frac_N1_tileable_40nm.xml
@@ -0,0 +1,448 @@
+<?xml version="1.0" ?><!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 1, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+--><architecture> 
+   <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  --> 
+   <models>  
+      <!-- A virtual model for I/O to be used in the physical mode of io block -->  
+      <model name="io">   
+         <input_ports>    
+            <port name="outpad"/>    
+         </input_ports>   
+         <output_ports>    
+            <port name="inpad"/>    
+         </output_ports>   
+      </model>  
+      <!-- A virtual model for I/O to be used in the physical mode of io block -->  
+      <model name="frac_lut4">   
+         <input_ports>    
+            <port name="in"/>    
+         </input_ports>   
+         <output_ports>    
+            <port name="lut3_out"/>    
+            <port name="lut4_out"/>    
+         </output_ports>   
+      </model>  
+   </models> 
+   <tiles>  
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->  
+      <tile name="io" area="0">   <sub_tile name="io" capacity="8">    
+          <equivalent_sites>     
+             <site pb_type="io"/>     
+          </equivalent_sites>    
+          <input name="outpad" num_pins="1"/>    
+          <output name="inpad" num_pins="1"/>    
+          <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
+          <pinlocations pattern="custom">     
+             <loc side="left">io.outpad io.inpad</loc>     
+             <loc side="top">io.outpad io.inpad</loc>     
+             <loc side="right">io.outpad io.inpad</loc>     
+             <loc side="bottom">io.outpad io.inpad</loc>     
+          </pinlocations>    
+       </sub_tile>  </tile>  
+      <tile name="clb" area="53894">   <sub_tile name="clb">    
+          <equivalent_sites>     
+             <site pb_type="clb"/>     
+          </equivalent_sites>    
+          <input name="I" num_pins="4" equivalent="full"/>    
+          <output name="O" num_pins="2" equivalent="none"/>    
+          <clock name="clk" num_pins="1"/>    
+          <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>    
+          <pinlocations pattern="spread"/>    
+       </sub_tile>  </tile>  
+   </tiles> 
+   <!-- ODIN II specific config ends --> 
+   <!-- Physical descriptions begin --> 
+   <layout tileable="true">  
+      <auto_layout aspect_ratio="1.0">   
+         <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->   
+         <perimeter type="io" priority="100"/>   
+         <corners type="EMPTY" priority="101"/>   
+         <!--Fill with 'clb'-->   
+         <fill type="clb" priority="10"/>   
+      </auto_layout>  
+      <fixed_layout name="2x2" width="4" height="4">   
+         <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->   
+         <perimeter type="io" priority="100"/>   
+         <corners type="EMPTY" priority="101"/>   
+         <!--Fill with 'clb'-->   
+         <fill type="clb" priority="10"/>   
+      </fixed_layout>  
+      <fixed_layout name="4x4" width="6" height="6">   
+         <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->   
+         <perimeter type="io" priority="100"/>   
+         <corners type="EMPTY" priority="101"/>   
+         <!--Fill with 'clb'-->   
+         <fill type="clb" priority="10"/>   
+      </fixed_layout>  
+   </layout> 
+   <device>  
+      <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->  
+      <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>  
+      <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->  
+      <area grid_logic_tile_area="0"/>  
+      <chan_width_distr>   
+         <x distr="uniform" peak="1.000000"/>   
+         <y distr="uniform" peak="1.000000"/>   
+      </chan_width_distr>  
+      <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>  
+      <connection_block input_switch_name="ipin_cblock"/>  
+   </device> 
+   <switchlist>  
+      <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->  
+      <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>  
+      <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->  
+      <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>  
+   </switchlist> 
+   <segmentlist>  
+      <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->  
+      <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->  
+      <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">   
+         <mux name="0"/>   
+         <sb type="pattern">1 1 1 1 1</sb>   
+         <cb type="pattern">1 1 1 1</cb>   
+      </segment>  
+   </segmentlist> 
+   <complexblocklist>  
+      <!-- Define I/O pads begin -->  
+      <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->  
+      <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->  
+      <pb_type name="io">   
+         <input name="outpad" num_pins="1"/>   
+         <output name="inpad" num_pins="1"/>   
+         <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->   
+         <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->   
+         <mode name="physical" disable_packing="true">    
+            <pb_type name="iopad" blif_model=".subckt io" num_pb="1">     
+               <input name="outpad" num_pins="1"/>     
+               <output name="inpad" num_pins="1"/>     
+            </pb_type>    
+            <interconnect>     
+               <direct name="outpad" input="io.outpad" output="iopad.outpad">      
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>      
+               </direct>     
+               <direct name="inpad" input="iopad.inpad" output="io.inpad">      
+                  <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>      
+               </direct>     
+            </interconnect>    
+         </mode>   
+
+         <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->   
+         <mode name="inpad">    
+            <pb_type name="inpad" blif_model=".input" num_pb="1">     
+               <output name="inpad" num_pins="1"/>     
+            </pb_type>    
+            <interconnect>     
+               <direct name="inpad" input="inpad.inpad" output="io.inpad">      
+                  <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>      
+               </direct>     
+            </interconnect>    
+         </mode>   
+         <mode name="outpad">    
+            <pb_type name="outpad" blif_model=".output" num_pb="1">     
+               <input name="outpad" num_pins="1"/>     
+            </pb_type>    
+            <interconnect>     
+               <direct name="outpad" input="io.outpad" output="outpad.outpad">      
+                  <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>      
+               </direct>     
+            </interconnect>    
+         </mode>   
+         <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->   
+         <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->   
+         <!-- Place I/Os on the sides of the FPGA -->   
+         <power method="ignore"/>   
+      </pb_type>  
+      <!-- Define I/O pads ends -->  
+      <!-- Define general purpose logic block (CLB) begin -->  
+      <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->  
+      <pb_type name="clb">   
+         <input name="I" num_pins="4" equivalent="full"/>   
+         <output name="O" num_pins="2" equivalent="none"/>   
+         <clock name="clk" num_pins="1"/>   
+         <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->   
+         <pb_type name="fle" num_pb="1">    
+            <input name="in" num_pins="4"/>    
+            <output name="out" num_pins="2"/>    
+            <clock name="clk" num_pins="1"/>    
+            <!-- Physical mode definition begin (physical implementation of the fle) -->    
+            <mode name="physical" disable_packing="true">     
+               <pb_type name="fabric" num_pb="1">      
+                  <input name="in" num_pins="4"/>      
+                  <output name="out" num_pins="2"/>      
+                  <clock name="clk" num_pins="1"/>      
+                  <pb_type name="frac_logic" num_pb="1">       
+                     <input name="in" num_pins="4"/>       
+                     <output name="out" num_pins="2"/>       
+                     <!-- Define LUT -->       
+                     <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">        
+                        <input name="in" num_pins="4"/>        
+                        <output name="lut3_out" num_pins="2"/>        
+                        <output name="lut4_out" num_pins="1"/>        
+                     </pb_type>       
+                     <interconnect>        
+                        <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>        
+                        <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>        
+                        <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->        
+                        <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>        
+                     </interconnect>       
+                  </pb_type>      
+                  <!-- Define flip-flop -->      
+                  <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">       
+                     <input name="D" num_pins="1" port_class="D"/>       
+                     <output name="Q" num_pins="1" port_class="Q"/>       
+                     <clock name="clk" num_pins="1" port_class="clock"/>       
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>       
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>       
+                  </pb_type>      
+                  <interconnect>       
+                     <direct name="direct1" input="fabric.in" output="frac_logic.in"/>       
+                     <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>       
+                     <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>       
+                     <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">        
+                        <!-- LUT to output is faster than FF to output on a Stratix IV -->        
+                        <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>        
+                        <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>        
+                     </mux>       
+                     <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">        
+                        <!-- LUT to output is faster than FF to output on a Stratix IV -->        
+                        <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>        
+                        <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>        
+                     </mux>       
+                  </interconnect>      
+               </pb_type>     
+               <interconnect>      
+                  <direct name="direct1" input="fle.in" output="fabric.in"/>      
+                  <direct name="direct2" input="fabric.out" output="fle.out"/>      
+                  <direct name="direct3" input="fle.clk" output="fabric.clk"/>      
+               </interconnect>     
+            </mode>    
+            <!-- Physical mode definition end (physical implementation of the fle) -->    
+            <!-- Dual 3-LUT mode definition begin -->    
+            <mode name="n2_lut3">     
+               <pb_type name="lut3inter" num_pb="1">      
+                  <input name="in" num_pins="3"/>      
+                  <output name="out" num_pins="2"/>      
+                  <clock name="clk" num_pins="1"/>      
+                  <pb_type name="ble3" num_pb="2">       
+                     <input name="in" num_pins="3"/>       
+                     <output name="out" num_pins="1"/>       
+                     <clock name="clk" num_pins="1"/>       
+                     <!-- Define the LUT -->       
+                     <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">        
+                        <input name="in" num_pins="3" port_class="lut_in"/>        
+                        <output name="out" num_pins="1" port_class="lut_out"/>        
+                        <!-- LUT timing using delay matrix -->        
+                        <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->        
+                        <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>        
+                     </pb_type>       
+                     <!-- Define the flip-flop -->       
+                     <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">        
+                        <input name="D" num_pins="1" port_class="D"/>        
+                        <output name="Q" num_pins="1" port_class="Q"/>        
+                        <clock name="clk" num_pins="1" port_class="clock"/>        
+                        <T_setup value="66e-12" port="ff.D" clock="clk"/>        
+                        <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>        
+                     </pb_type>       
+                     <interconnect>        
+                        <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>        
+                        <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">         
+                           <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->         
+                           <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>         
+                        </direct>        
+                        <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>        
+                        <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">         
+                           <!-- LUT to output is faster than FF to output on a Stratix IV -->         
+                           <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>         
+                           <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>         
+                        </mux>        
+                     </interconnect>       
+                  </pb_type>      
+                  <interconnect>       
+                     <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>       
+                     <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>       
+                     <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>       
+                     <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>       
+                  </interconnect>      
+               </pb_type>     
+               <interconnect>      
+                  <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>      
+                  <direct name="direct2" input="lut3inter.out" output="fle.out"/>      
+                  <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>      
+               </interconnect>     
+            </mode>    
+            <!-- Dual 3-LUT mode definition end -->    
+            <!-- 4-LUT mode definition begin -->    
+            <mode name="n1_lut4">     
+               <!-- Define 4-LUT mode -->     
+               <pb_type name="ble4" num_pb="1">      
+                  <input name="in" num_pins="4"/>      
+                  <output name="out" num_pins="1"/>      
+                  <clock name="clk" num_pins="1"/>      
+                  <!-- Define LUT -->      
+                  <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">       
+                     <input name="in" num_pins="4" port_class="lut_in"/>       
+                     <output name="out" num_pins="1" port_class="lut_out"/>       
+                     <!-- LUT timing using delay matrix -->       
+                     <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->       
+                     <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>       
+                  </pb_type>      
+                  <!-- Define flip-flop -->      
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">       
+                     <input name="D" num_pins="1" port_class="D"/>       
+                     <output name="Q" num_pins="1" port_class="Q"/>       
+                     <clock name="clk" num_pins="1" port_class="clock"/>       
+                     <T_setup value="66e-12" port="ff.D" clock="clk"/>       
+                     <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>       
+                  </pb_type>      
+                  <interconnect>       
+                     <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>       
+                     <direct name="direct2" input="lut4.out" output="ff.D">        
+                        <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->        
+                        <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>        
+                     </direct>       
+                     <direct name="direct3" input="ble4.clk" output="ff.clk"/>       
+                     <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">        
+                        <!-- LUT to output is faster than FF to output on a Stratix IV -->        
+                        <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>        
+                        <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>        
+                     </mux>       
+                  </interconnect>      
+               </pb_type>     
+               <interconnect>      
+                  <direct name="direct1" input="fle.in" output="ble4.in"/>      
+                  <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>      
+                  <direct name="direct3" input="fle.clk" output="ble4.clk"/>      
+               </interconnect>     
+            </mode>    
+            <!-- 6-LUT mode definition end -->    
+         </pb_type>   
+         <interconnect>    
+            <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->    
+            <complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in">     
+               <delay_constant max="95e-12" in_port="clb.I" out_port="fle[0:0].in"/>     
+               <delay_constant max="75e-12" in_port="fle[0:0].out" out_port="fle[0:0].in"/>     
+            </complete>    
+            <complete name="clks" input="clb.clk" output="fle[0:0].clk">
+        </complete>    
+            <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->    
+            <direct name="clbouts1" input="fle[0:0].out[0:0]" output="clb.O[0:0]"/>    
+            <direct name="clbouts2" input="fle[0:0].out[1:1]" output="clb.O[1:1]"/>    
+         </interconnect>   
+         <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->   
+         <!-- Place this general purpose logic block in any unspecified column -->   
+      </pb_type>  
+      <!-- Define general purpose logic block (CLB) ends -->  
+   </complexblocklist> 
+</architecture>