add mcnc big20 test cases and start debugging
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tangxifan
parent
95863e996a
commit
f76a3090c4
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>
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This is flip-flop with scan-chain feature.
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When the TESTEN is enabled, the data will be propagated form DI instead of D
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-->
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<circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="D_chain" lib_name="DI" size="1"/>
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<port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
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<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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<port type="input" prefix="outpad" size="1"/>
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<port type="output" prefix="inpad" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="input" prefix="cin" size="1"/>
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<port type="output" prefix="sumout" size="1"/>
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<port type="output" prefix="cout" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="adder_carry" circuit_model_name="direct_interc"/>
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<direct name="scff_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
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<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
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<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'n2_lut5' -->
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:4]"/>
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<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
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<!-- Binding operating pb_types in mode 'arithmetic' -->
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].frac_logic.adder_phy"/>
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<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
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<!-- Binding operating pb_types in mode 'ble6' -->
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="00">
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<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:5]"/>
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<port name="out" physical_mode_port="lut6_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
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<!-- Binding operating pb_types in mode 'shift_register' -->
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<pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
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<!-- End physical pb_type binding in complex block CLB -->
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</pb_type_annotations>
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</openfpga_architecture>
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<openfpga_simulation_setting>
|
||||||
|
<clock_setting>
|
||||||
|
<!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
|
||||||
|
<operating frequency="200e6" num_cycles="auto" slack="0.2"/>
|
||||||
|
<programming frequency="10e6"/>
|
||||||
|
</clock_setting>
|
||||||
|
<simulator_option>
|
||||||
|
<operating_condition temperature="25"/>
|
||||||
|
<output_log verbose="false" captab="false"/>
|
||||||
|
<accuracy type="abs" value="1e-13"/>
|
||||||
|
<runtime fast_simulation="true"/>
|
||||||
|
</simulator_option>
|
||||||
|
<monte_carlo num_simulation_points="2"/>
|
||||||
|
<measurement_setting>
|
||||||
|
<slew>
|
||||||
|
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
||||||
|
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
||||||
|
</slew>
|
||||||
|
<delay>
|
||||||
|
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||||
|
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||||
|
</delay>
|
||||||
|
</measurement_setting>
|
||||||
|
<stimulus>
|
||||||
|
<clock>
|
||||||
|
<rise slew_type="abs" slew_time="20e-12" />
|
||||||
|
<fall slew_type="abs" slew_time="20e-12" />
|
||||||
|
</clock>
|
||||||
|
<input>
|
||||||
|
<rise slew_type="abs" slew_time="25e-12" />
|
||||||
|
<fall slew_type="abs" slew_time="25e-12" />
|
||||||
|
</input>
|
||||||
|
</stimulus>
|
||||||
|
</openfpga_simulation_setting>
|
||||||
|
|
@ -0,0 +1,134 @@
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# Configuration file for running experiments
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||||
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||||
|
# timeout_each_job is timeout for each job
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
|
||||||
|
[GENERAL]
|
||||||
|
run_engine=openfpga_shell
|
||||||
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
|
||||||
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
|
power_analysis = true
|
||||||
|
spice_output=false
|
||||||
|
verilog_output=true
|
||||||
|
timeout_each_job = 20*60
|
||||||
|
fpga_flow=vpr_blif
|
||||||
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
|
||||||
|
|
||||||
|
[ARCHITECTURES]
|
||||||
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
|
||||||
|
|
||||||
|
[BENCHMARKS]
|
||||||
|
# Pass
|
||||||
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
|
||||||
|
# Pass, but port does not match, i_15_ is dangling
|
||||||
|
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
|
||||||
|
# Pass
|
||||||
|
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
|
||||||
|
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
|
||||||
|
# To be tested
|
||||||
|
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
|
||||||
|
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
|
||||||
|
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
|
||||||
|
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
|
||||||
|
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
|
||||||
|
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
|
||||||
|
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
|
||||||
|
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
|
||||||
|
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
|
||||||
|
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
|
||||||
|
# Pass
|
||||||
|
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
|
||||||
|
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
|
||||||
|
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
|
||||||
|
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
|
||||||
|
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
|
||||||
|
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
|
||||||
|
|
||||||
|
[SYNTHESIS_PARAM]
|
||||||
|
# Benchmark alu4
|
||||||
|
bench0_top = alu4
|
||||||
|
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act
|
||||||
|
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v
|
||||||
|
# Benchmark apex2
|
||||||
|
bench1_top = apex2
|
||||||
|
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
|
||||||
|
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
|
||||||
|
# Benchmark apex4
|
||||||
|
bench2_top = apex4
|
||||||
|
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act
|
||||||
|
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v
|
||||||
|
# Benchmark bigkey
|
||||||
|
bench3_top = bigkey
|
||||||
|
bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act
|
||||||
|
bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v
|
||||||
|
# Benchmark clma
|
||||||
|
bench4_top = clma
|
||||||
|
bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act
|
||||||
|
bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v
|
||||||
|
# Benchmark des
|
||||||
|
bench5_top = des
|
||||||
|
bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act
|
||||||
|
bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v
|
||||||
|
# Benchmark diffeq
|
||||||
|
bench6_top = diffeq
|
||||||
|
bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act
|
||||||
|
bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v
|
||||||
|
# Benchmark dsip
|
||||||
|
bench7_top = dsip
|
||||||
|
bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act
|
||||||
|
bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v
|
||||||
|
# Benchmark elliptic
|
||||||
|
bench8_top = elliptic
|
||||||
|
bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act
|
||||||
|
bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v
|
||||||
|
# Benchmark ex1010
|
||||||
|
bench9_top = ex1010
|
||||||
|
bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act
|
||||||
|
bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v
|
||||||
|
# Benchmark ex5p
|
||||||
|
bench10_top = ex5p
|
||||||
|
bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act
|
||||||
|
bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v
|
||||||
|
# Benchmark frisc
|
||||||
|
bench11_top = frisc
|
||||||
|
bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act
|
||||||
|
bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v
|
||||||
|
# Benchmark misex3
|
||||||
|
bench12_top = misex3
|
||||||
|
bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act
|
||||||
|
bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v
|
||||||
|
# Benchmark pdc
|
||||||
|
bench13_top = pdc
|
||||||
|
bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act
|
||||||
|
bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v
|
||||||
|
# Benchmark s298
|
||||||
|
bench14_top = s298
|
||||||
|
bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
|
||||||
|
bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
|
||||||
|
# Benchmark s38417
|
||||||
|
bench15_top = s38417
|
||||||
|
bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act
|
||||||
|
bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v
|
||||||
|
# Benchmark s38584
|
||||||
|
bench16_top = s38584
|
||||||
|
bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act
|
||||||
|
bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v
|
||||||
|
# Benchmark seq
|
||||||
|
bench17_top = seq
|
||||||
|
bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act
|
||||||
|
bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v
|
||||||
|
# Benchmark spla
|
||||||
|
bench18_top = spla
|
||||||
|
bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act
|
||||||
|
bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v
|
||||||
|
# Benchmark tseng
|
||||||
|
bench19_top = tseng
|
||||||
|
bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act
|
||||||
|
bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v
|
||||||
|
|
||||||
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
#end_flow_with_test=
|
||||||
|
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||||
Loading…
Reference in New Issue