diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
new file mode 100644
index 000000000..74d1d9933
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
@@ -0,0 +1,231 @@
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12 5e-12
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+ 10e-12 5e-12
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+ 10e-12 5e-12 5e-12
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+ 10e-12 5e-12 5e-12
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diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf
index 08a28be87..7eb80e932 100644
--- a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf
@@ -15,12 +15,12 @@ spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
[ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
[BENCHMARKS]
#
diff --git a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
new file mode 100644
index 000000000..a31984e8b
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
@@ -0,0 +1,441 @@
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
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+ 1 1 1 1 1
+ 1 1 1 1
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+ 235e-12
+ 235e-12
+ 235e-12
+ 235e-12
+ 235e-12
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
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