diff --git a/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_flatten/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_flatten/config/task.conf
index bcaad37ce..dbd1c3db8 100644
--- a/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_flatten/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_flatten/config/task.conf
@@ -16,7 +16,7 @@ timeout_each_job = 20*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=
diff --git a/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register/config/task.conf
index 9974313fd..1bb51ba34 100644
--- a/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register/config/task.conf
@@ -16,7 +16,7 @@ timeout_each_job = 20*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml